4

Codec Integration

Fig.3 Recommended External Components

Fig.2 System Configuration Diagram – showing the FX629, which with the indicated interfacing, will conform to

the Mil-Std-188-113 Specification

ANALOGUE

INPUT

INTERFACE

(BALUN

&

BUFFER)

SYSTEM

INPUT

SYSTEM

OUTPUT

REGULATED POWER

SUPPLY

SYNCHRONOUS CLOCK

AND

DATA SYSTEM

FX629 PARAMETERS

MEASURED HERE

FX629 PARAMETERS

MEASURED HERE

1.024 MHz

1.024 MHz

DATA

CLOCK MODE

16/32/64kb/s

ANALOGUE

OUTPUT

INTERFACE

(BALUN

&

BUFFER)

FX629

ENCODER

FX629

DECODER

DATA

CLOCKS

CLOCKS

Component

Unit Value

R

1

1M

Oscillator Inverter bias resistor.

R

2

Selectable

Xtal Drive limiting resistor.

C

1

33p

Xtal Circuit drain capacitor.

C

2

33p

Xtal Circuit gate capacitor.

C

3

1.0

µ

Encoder Input coupling capacitor – The drive source impedance to this

input should be less than 100

Ω. Output Idle channel noise levels will

improve with an even lower source impedance.

C

4

1.0

µ

Bias decoupling capacitor.

C

5

1.0

µ

V

X

1

1.024 MHz

A 1.024 MHz Xtal/clock input will yield exactly 16/32/64 kb/s data clock

rates. Xtal circuitry shown is in accordance with CML application note

D/XT/1 April 1986.

Tolerance :– Resistors

± 10% Capacitors ± 20%

FX629J

1

2

3

4

5

6

7

8

9

10

11

22

21

20

19

18

17

16

15

14

13

12

R

1

R

2

C

2

C

1

X

1

XTAL/CLOCK

XTAL

N/C

ENCODER DATA CLOCK

ENCODER OUTPUT

DATA ENABLE

N/C

BIAS

ENCODER INPUT

C

3

C

4

CLOCK MODE 1

CLOCK MODE 2

ALGORITHM

DECODER DATA CLOCK

DECODER INPUT

DECODER FORCE IDLE

POWERSAVE

N/C

DECODER OUTPUT

N/C

C

5

ENCODER FORCE IDLE

SS

V