33874 datasheet(15/38 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33874

FUNCTIONAL DESCRIPTION

INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

The 33874 is one in a family of devices designed for low-

voltage automotive and industrial lighting and motor control

applications. Its four low RDS(ON) MOSFETs (35mΩ) can

control the high sides of four separate resistive or inductive

loads.

Programming, control, and diagnostics are accomplished

using a 16-bit SPI interface. Additionally, each output has its

own parallel input for PWM control if desired. The 33874

allows the user to program via the SPI the fault current trip

levels and duration of acceptable lamp inrush or motor stall

intervals. Such programmability allows tight control of fault

currents and can protect wiring harnesses and circuit boards

as well as loads.

The 33874 is packaged in a power-enhanced 12 x 12

nonleaded PQFN package with exposed tabs.

FUNCTIONAL PIN DESCRIPTION

OUTPUT CURRENT MONITORING (CSNS)

The Current Sense pin sources a current proportional to

the designated HS0:HS3 output. That current is fed into a

ground-referenced resistor and its voltage is monitored by an

MCU's A/D. The output to be monitored is selected via the

SPI. This pin can be tri-stated through the SPI.

SERIAL INPUTS (IN0, IN1, IN2, IN3)

The IN0:IN3 high side input pins are used to directly

control HS0:HS3 high side output pins, respectively. A SPI

logic state is ORed or ANDed with the SPI instruction. These

pins are to be driven with 5.0V CMOS levels, and they have

an active internal pull-down current source.

TEMPERATURE FEEDBACK (TEMP)

This pin reports an analog voltage value proportional to the

temperature of the GND. It is used by the MCU to monitor

board temperature.

FAULT STATUS (FS)

This pin is an open drain configured output requiring an

external pull-up resistor to VDD for fault reporting. If a device

fault condition is detected, this pin is active LOW. Specific

device diagnostic faults are reported via the SPI SO pin.

WAKE

This input pin controls the device mode and watchdog

timeout feature if enabled. An internal clamp protects this pin

from high damaging voltages when the output is current

limited with an external resistor. This input has a passive

internal pull-down.

RESET (RST)

This input pin is used to initialize the device configuration

and fault registers, as well as place the device in a low-

current sleep mode. The pin also starts the watchdog timer

when transitioning from logic [0] to logic [1]. This pin should

not be allowed to be logic [1] until VDD is in regulation. This

pin has a passive internal pull-down.

CHIP SELECT (CS)

The CS pin enables communication with the master

microcontroller (MCU). When this pin is in a logic [0] state,

the device is capable of transferring information to, and

receiving information from, the MCU. The 33874 latches in

data from the Input Shift registers to the addressed registers

on the rising edge of CS. The device transfers status

information from the power output to the Shift register on the

falling edge of CS. The SO output driver is enabled when CS

is logic [0]. CS should transition from a logic [1] to a logic [0]

state only when SCLK is a logic [0]. CS has an active internal

pull-up, IUP.

SERIAL CLOCK (SCLK)

The SCLK pin clocks the internal shift registers of the

33874 device. The serial input (SI) pin accepts data into the

input shift register on the falling edge of the SCLK signal

while the serial output (SO) pin shifts data information out of

the SO line driver on the rising edge of the SCLK signal. It is

important the SCLK pin be in a logic low state whenever CS

makes any transition. For this reason, it is recommended the

SCLK pin be in a logic [0] whenever the device is not

accessed (CS logic [1] state). SCLK has an active internal

pull-down. When CS is logic [1], signals at the SCLK and SI

pins are ignored and SO is tri-stated (high-impedance) (see

Figure 9, page 18).

SERIAL INPUT (SI)

This is a serial interface (SI) command data input pin.

Each SI bit is read on the falling edge of SCLK. A 16-bit

stream of serial data is required on the SI pin, starting with

D15 to D0. The internal registers of the 33874 are configured

and controlled using a 5-bit addressing scheme described in

Table 8, page 22. Register addressing and configuration are

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