PIC12F752 datasheet(149/204 Pages) MICROCHIP

149 / 204 page

 2011 Microchip Technology Inc.

Preliminary

DS41576A-page 149

PIC12F752/HV752

17.5

Context Saving During Interrupts

During an interrupt, only the return PC value is saved

on the stack. Typically, users may wish to save key

registers during an interrupt (e.g., W and STATUS

registers). This must be implemented in software.

Temporary

holding

registers

W_TEMP

and

STATUS_TEMP should be placed in the last 16 bytes

of GPR (see Figure 2-2). These 16 locations are

common to all banks and do not require banking. This

makes context save and restore operations simpler.

The code shown in Example 17-1 can be used to:

• Store the W register

• Store the STATUS register

• Execute the ISR code

• Restore the Status (and Bank Select Bit register)

• Restore the W register

EXAMPLE 17-1:

SAVING STATUS AND W REGISTERS IN RAM

17.6

Watchdog Timer (WDT)

The Watchdog Timer is a free running timer, using

LFINTOSC oscillator as its clock source. The WDT is

enabled by setting the WDTE bit of the Configuration

Word (default setting). When WDTE is set, the

LFINTOSC will always be enabled to provide a clock

source to the WDT module.

During normal operation, a WDT time-out generates a

device Reset. If the device is in Sleep mode, a WDT

time-out causes the device to wake-up and continue

with normal operation.

The

WDT

can

permanently

disabled

programming the Configuration bit, WDTE, as clear

(Section 17.1 “Configuration Bits”).

17.6.1

WDT PERIOD

The WDT has a nominal time-out period of 18 ms (with

prescaler).

The

time-out

periods

vary

with

temperature, VDD and process variations from part to

part (see DC specs). If longer time-out periods are

desired, a prescaler with a division ratio of up to 1:128

can be assigned to the WDT under software control by

writing to the OPTION register. Thus, time-out periods

up to 2.3 seconds can be realized.

The CLRWDT and SLEEP instructions clear the WDT

and the prescaler, if assigned to the WDT, and prevent

it from timing out and generating a device Reset.

The TO bit in the STATUS register will be cleared upon

a Watchdog Timer time-out.

Note:

The PIC12F752/HV752 does not require

saving the PCLATH. However, if com-

puted GOTOs are used in both the ISR and

the main code, the PCLATH must be

saved and restored in the ISR.

MOVWF

W_TEMP

;Copy W to TEMP register

SWAPF

STATUS,W

;Swap status to be saved into W

;Swaps are used because they do not affect the status bits

MOVWF

STATUS_TEMP

;Save status to bank zero STATUS_TEMP register

:(ISR)

;Insert user code here

SWAPF

STATUS_TEMP,W

;Swap STATUS_TEMP register into W

;(sets bank to original state)

MOVWF

STATUS

;Move W into STATUS register

SWAPF

W_TEMP,F

;Swap W_TEMP

SWAPF

W_TEMP,W

;Swap W_TEMP into W

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