SM5M2

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Program Counter PC and Stack Register SR

A ROM address is specified by the program

counter (PC). The PC comprises 12-bit where 6-

The table reference instruction PAT executes a

similar operation to that of the subroutine jump and

uses one level of the stack register.

Program Memory (ROM)

The ROM is used for program storage. The ROM

capacity of the SM5M2 is 3 072-step . The ROM

is organized into 48-page where one page is

organized into 64-step.

Program counter PC

Push

Pop

SR ( level 1 )

SR ( level 2 )

SR ( level 3 )

SR ( level 4 )

MSB

LSB

Stack register SR

Page

Step

Fig. 6

Program Counter PC and Stack Register SR

000000

Program

start

First page

of

subroutine

TRS

Interrupt Standby

release

Table

reference

page PAT

000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111

010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111

100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111

Last page

Fig. 7

ROM Organization