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SM5M2 Datasheet(PDF) 19 Page - Sharp Corporation

Part # SM5M2
Description  4-Bit Single-Chip Microcomputer(LCD Driver)
PDF  28 Pages
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Manufacturer  SHARP [Sharp Corporation]
Direct Link  http://sharp-world.com/
Logo SHARP - Sharp Corporation

SM5M2 Datasheet(HTML) 19 Page - Sharp Corporation

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SM5M2
- 19 -
TRANSITION FROM THE OPERATION MODE TO THE
STANDBY MODE
The HALT instruction is executed to set the halt
mode and the STOP instruction is executed to set
the stop mode.
Since the interrupt is used to release from the
standby mode, the mode does not transfer to the
standby mode if any of the following conditions are
satisfied during execution of the STOP or HALT
instruction.
a) RE0 is set and the INTA level is High.
b) RE2 is set and the IFD flag is set.
If any of the conditions above is satisfied, the
mode does not transfer to the standby mode even
if the STOP or HALT instruction is executed and
the instruction at the address following that of the
STOP or HALT instruction is executed. Therefore,
place the JUMP instruction which specifies step 0
on page 3 to the location at the address following
that of the STOP or HALT instruction.
RELEASE FROM THE STANDBY MODE TO THE
OPERATION MODE
Release based on an interrupt request from the
INTA pin or divider overflow. However, the reset or
any port High in Port 1 is limited to a nonmaskable
interrupt request.
The program restarts from step 0 on page 3.
However, if the IME flag is set, the instruction at
step 0 on page 3 is executed and a subroutine
jump is performed to the interrupt processing
routine specified on page 2 according to the type
of interrupt.
Even if Low level input on INTA pin is removed
before 900 command cycles, the stop mode is
released.
However, the program will not jump to 20H page
(interrupt process routine).
Interrupt request flag IFA is not set : the program
continues at step 0 of page 3.
Interrupts
Interrupts originate from an INTA input or divider
overflow. The IFA and IFD flags become interrupt
request flags.
The interrupt block is composed of mask flags
(RE0, RE2), the IME flag and interrupt processing
circuit.
As shown in Fig. 11, resetting a mask flag enables
the interrupt request flag to be independently
masked. Thus, the mask flags can be used in a
program to establish the interrupt priority.
The
priority for interrupts generated simultaneously is
shown in Table 6.
During the standby mode, the contents of the RAM
and stack RAM are retained. The contents of the
flags, registers and output latches shown below are
also retained.
A release from the standby mode to the operation
mode is performed by a reset port input, an interrupt
from the nonmaskable INTA, any port High in Port 1,
and divider. A maskable interrupt request cannot
become a factor in releasing back to the operation
mode. The mask setting is performed with RE
register. (see Table 1)
CAUTION :
When all of P10 to P13 level are High, the SM5M2 is
performed to release the standby mode and enter normally
hardware reset operation. (Mask option)
FLAG
IFA flag
IFD flag
IME flag
C flag
P33 flag
REGISTER
ACC
X register
BM, BL register
SB register
OUTPUT LATCH REGISTER
P0 register
P1 register
P2 register
SP
SR
RC, RD, RE, RF



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