SM5M2 datasheet(20/28 Pages) SHARP

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SM5M2

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Table 6

Interrupt Event Summary

When the IME flag is set, the interrupt circuit

activates according to the interrupt request and a

subroutine jump is performed to the specified

address.

The jump destinations according to

interrupt origin are shown in Table 6. When the

IME flag is cleared, an interrupt is not accepted

even if an interrupt request is generated.

The

interrupt timing is shown in Fig. 12 and Fig. 13.

The timing chart shown in Fig. 12 shows the

interrupt enable state when an interrupt request

has been generated. In this case, the interrupt

processing signal INT goes High, one instruction

cycle after the interrupt request flag is set. When

INT goes High, the contents of the program

counter are pushed into the stack register and

execution jumps to the specified address. At this

time, the INT signal and the IME flag are cleared to

establish the interrupt disable mode. The IME flag

is set again when the RTNI instruction is executed

to establish the interrupt enable mode.

The timing chart shown in Fig. 13 shows the state

when

interrupts

are

enabled

while

multiple

interrupts are generated. In this case, a subroutine

jump is performed according to the interrupt having

the highest priority. When returning from the

subroutine by executing the RTNI instruction, the

instruction (two words are executed for a two-word

instruction) at the location of return is executed and

the interrupt for the next highest priority is

accepted.

If an interrupt request is generated during execution

of a two-cycle instruction, the instruction is

executed after which interrupt processing is

performed.

If consecutive LAX instructions are

skipped or if the SKIP conditions are satisfied, the

skip operation is terminated after which interrupt

processing is performed.

INTERRUPT REQUEST

(REQUEST FLAG)

JUMP DESTINATION

PRIORITY

ORDER

INTERRUPT

ENABLE FLAG

PAGE

STEP

INTA input (IFA)

RE0

Divider overflow (IFD)

RE2

IFA

IFD

IME

RE2

RE0

Stack register

Program counter

INT signal

Interrupt

processing

circuit

Interrupt enable flag

Interrupt request

flags

Mask flags

Fig. 11

Interrupt Block

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