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HT1382 Datasheet(PDF) 6 Page - Holtek Semiconductor Inc |
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HT1382 Datasheet(HTML) 6 Page - Holtek Semiconductor Inc |
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6 / 29 page  I 2C Interface Symbol Parameter Remark Min. Typ. Max. Unit f SCL Clock frequency ¾¾ ¾ 400 kHz t HIGH Clock High Time ¾ 600 ¾¾ ns t LOW Clock Low Time ¾ 1300 ¾¾ ns t r SDA and SCL Rise Time Note ¾¾ 300 ns t f SDA and SCL Fall Time Note ¾¾ 300 ns t HD:STA START Condition Hold Time After this period, the first clock pulse is generated. 600 ¾¾ ns t SU:STA START Condition Setup Time Only relevant for repeated START condition. 600 ¾¾ ns t HD:DAT Data Input Hold Time ¾ 0 ¾¾ ns t SU:DAT Data Input Setup Time ¾ 100 ¾¾ ns t SU:STO STOP Condition Setup Time ¾ 600 ¾¾ ns t AA Output Valid from Clock ¾¾ ¾ 900 ns t BUF Bus Free Time Time in which the bus must be free before a new transmission can start 1300 ¾¾ ns t SP Input Filter Time Constant (SDA and SCL Pins) Noise suppression time ¾¾ 50 ns Note: These parameters are periodically sampled but not 100% tested 3-wire Interface Ta= -40°C~85°C Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions f SCLK Serial Clock 3V ¾¾ ¾ 1 MHz 5V ¾¾ ¾ 2 MHz t DC Data to Clock Setup 3V ¾ 100 ¾¾ ns 5V ¾ 50 ¾¾ ns t CDH Clock to Data Hold 3V ¾ 140 ¾¾ ns 5V ¾ 70 ¾¾ ns t CDD Clock to Data Delay 3V ¾¾ ¾ 400 ns 5V ¾¾ ¾ 200 ns t CL Clock Low Time 3V ¾ 500 ¾¾ ns 5V ¾ 250 ¾¾ ns t CH Clock High Time 3V ¾ 500 ¾¾ ns 5V ¾ 250 ¾¾ ns t r Clock Rise and Fall time 3V ¾¾ ¾ 1000 ns t f 5V ¾¾ ¾ 500 ns Rev. 1.40 6 May 27, 2011 HT1382 I2C/3-Wire Real Time Clock |
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