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MAX11329–MAX11332

3Msps, 12-/10-Bit, 8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

ELECTRICAL CHARACTERISTICS (MAX11329/MAX11330) (continued)

Parts are tested with MUX externally connected to the ADC input.

Note 3: Channel ID disabled.

Note 4: Tested in single-ended mode.

Note 5: Offset nulled.

Note 7: Tested and guaranteed with fully differential input.

Note 8: Conversion time is defined as the number of clock cycles multiplied by the clock period with a 50% duty cycle.

Note 10: See Figure 3 (Equivalent Input Circuit).

Note 11: Guaranteed by characterization.

Figure 1. Detailed Serial-Interface Timing Diagram

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

SCLK Rise to DIN Hold

1

ns

CS Fall to SCLK Fall Setup

4

ns

SCLK Fall to CS Fall Hold

1

ns

CNVST Pulse Width

See Figure 6

5

ns

CS or CNVST Rise to EOC Low

(Note 7)

1.7

2.4

F

s

CS Pulse Width

5

ns

CS

SCLK

DIN

DOUT

16TH

CLOCK

1ST

CLOCK