MAX11329 datasheet(3/37 Pages) MAXIM

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�� Maxim Integrated Products 3

MAX11329–MAX11332

3Msps, 12-/10-Bit, 8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

ELECTRICAL CHARACTERISTICS (MAX11331/MAX11332) (continued)

(VDD = 2.35V to 3.6V, VOVDD = 1.5V to 3.6V, fSAMPLE = 3Msps, fSCLK = 48MHz, 50% duty cycle, VREF+ = VDD, TA = -40NC to +125NC,

unless otherwise noted. Typical values are at TA = +25NC.) (Note 2)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Crosstalk

-0.5dB below full-scale of 99.2432kHz

sine wave input to the channel being

sampled, apply full-scale 69.2139kHz

sine wave signal to all 15 nonselected

input channels.

-88

CONVERSION RATE

Power-Up Time

tPU

Conversion cycle, external clock

Cycles

Acquisition Time

tACQ

Conversion Time

tCONV

Internally clocked (Note 8)

2.1

µs

Externally clocked, fSCLK = 48MHz,

16 cycles (Note 8)

333

External Clock Frequency

fSCLK

0.48

MHz

Aperture Delay

Aperture Jitter

RMS

ANALOG INPUT

Input Voltage Range

VINA

Unipolar, (single ended and pseudo-

differential)

VREF+

Bipolar

(Note 9)

Range bit set to 0

-VREF+/2

VREF+/2

Range bit set to 1

-VREF+

VREF+

Absolute Input Voltage Range

AIN+, AIN- relative to GND

-0.1

VREF+ + 0.1

Static Input Leakage Current

IILA

VAIN = VDD, GND

-0.01

1.5

Input Capacitance

CAIN

During acquisition time;

RANGE bit = 0 (Note 10)

During acquisition time;

RANGE bit = 1 (Note 10)

7.5

EXTERNAL REFERENCE INPUT

REF- Input Voltage Range

VREF-

-0.3

REF+ Input Voltage Range

VREF+

VDD + 50mV

REF+ Input Current

IREF+

VREF+ = 2.5V, fSAMPLE = 3Msps

110

VREF+ = 2.5V, fSAMPLE = 0Msps

0.1

DIGITAL INPUTS (SCLK, DIN, CS, CNVST)

Input Voltage Low

VIL

VOVDD

0.25

Input Voltage High

VIH

VOVDD

0.75

Input Hysteresis

VHYST

VOVDD

0.15

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