MAX11329 datasheet(31/37 Pages) MAXIM

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�� Maxim Integrated Products 31

MAX11329–MAX11332

3Msps, 12-/10-Bit, 8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Figure 10. SampleSet Timing Diagram

Applications Information

How to Program Modes

1) Configure the ADC (set the MSB on DIN to 1).

2) Program ADC mode control (set the MSB on DIN to 0)

to begin the conversion process or to control power

management features.

• IfADCmodecontroliswrittenduringaconversion

sequence, the ADC finishes the present conver-

sion and at the next falling edge of CS initiates its

new instruction.

• Ifconfigurationdata(MSBonDINisa1)iswritten

during a conversion sequence, the ADC finishes

the present conversion in the existing scan mode.

However, data on DOUT is not valid in following

frames until a new ADC mode control instruction

is coded.

Programming Sequence Flow Chart

See Figure 11 for programming sequence.

Layout, Grounding, and Bypassing

For best performance, use PCBs with a solid ground

plane. Ensure that digital and analog signal lines are

separated from each other. Do not run analog and digital

(especially clock) lines parallel to one another or digital

lines underneath the ADC package. Noise in the VDD,

OVDD, and REF affects the ADC’s performance. Bypass

the VDD, OVDD, and REF to ground with 0.1FF and 10FF

bypass capacitors. Minimize capacitor lead and trace

lengths for best supply-noise rejection.

Choosing an Input Amplifier

It is important to match the settling time of the input

amplifier to the acquisition time of the ADC. The conver-

sion results are accurate when the ADC samples the

input signal for an interval longer than the input signal’s

worst-case settling time. By definition, settling time is the

interval between the application of an input voltage step

and the point at which the output signal reaches and

stays within a given error band centered on the result-

ing steady-state amplifier output level. The ADC input

sampling capacitor charges during the sampling cycle,

referred to as the acquisition period. During this acquisi-

tion period, the settling time is affected by the input resis-

tance and the input sampling capacitance. This error

can be estimated by looking at the settling of an RC time

constant using the input capacitance and the source

impedance over the acquisition time period. Figure 13

shows a typical application circuit. The MAX4430, offer-

ing a settling time of 37ns at 16-bit resolution, is an excel-

lent choice for this application.

Table 15 lists serveral recommended operational ampli-

fiers for MAX11129–MAX11132.

SCLK

DIN

ENTRY 1

WRITE SampleSet REGISTER

DEFINE SEQ_LENGTH

WRITE ADC MODE CONTROL

OR CONTINUE WITH ADDITIONAL

CONFIGURATION SETTINGS

ENTRY 2

ENTRY N = (SEQ_LENGTH)

DOUT

LOAD SampleSet PATTERN

TIME BETWEEN CS FALLING AND

RISING EDGE DEPENDS IN SEQ_LENGTH

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