DM9010BI datasheet(12/60 Pages) DAVICOM

12 / 60 page

DM9010BI

Industrial-temperature Single Chip Ethernet Controller with General Processor Interface

Preliminary

Version: DM9010BI--DS-P01

January 12, 2010

5.6 10/100 PHY/Fiber

Fiber-optic Signal Detect

PECL signal, which indicates whether or not the fiber-optic receive pair is

receiving valid levels

BGGND

Band gap Ground, need to connect to AGND.

BGRES

I/O

Band gap Pin

27,28

RXVDD18

Internal regulator 1.8V output for TP RX

RXI+

I/O

TP RX Input

RXI-

I/O

TP RX Input

RXGND

RX Ground

TXGND

TX Ground

TXO+

I/O

TP TX Output

TXO-

I/O

TP TX Output

TXVDD18

Internal regulator 1.8V output for TP TX

5.7 Miscellaneous

16,17,18,

TEST1~TEST4

Operation Mode

Test 1, 2, 3, 4 = (1, 1, 0, 0) in normal application

TEST5

I,PD Internal system clock source

0: use internal 50MHz clock *(Suggestion)

1: use CLK20MO pin

68,69,70,

71,

74,75,77

GP0~6

I/O,PD General I/O Ports

Registers GPCR and GPR can program these pins

The GPIO0 is an output mode, and output data high at default is to power

down internal PHY and other external MII device

GP1~3 defaults are input ports, GP 0, 4~6 force to output ports.

LINK_O

O,PD Cable Link Status Output. Active High

This pin is also used as a strap pin to define whether the MII interface is a

reversed MII interface (pulled high) or a normal MII interface (not pulled

high). This pin has a pulled down resistor about 60k ohm internally.

WAKE

O,PD Issue a wake up signal when wake up event happens

This pin has a pulled down resistor about 60k ohm internally.

PW_RST#

Power on Reset

Active low signal to initiate the DM9010BI

The DM9010BI is ready after 5us when this pin deasserted

DM9010BI Datasheet(PDF) 12 Page - Davicom Semiconductor, Inc.

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