Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

DM9010BI Datasheet(PDF) 24 Page - Davicom Semiconductor, Inc.

Part # DM9010BI
Description  Industrial-temperature 10/100 Mbps Single Chip Ethernet Controller With General Processor Interface
PDF  60 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  DAVICOM [Davicom Semiconductor, Inc.]
Direct Link  http://www.davicom.com.tw
Logo DAVICOM - Davicom Semiconductor, Inc.

DM9010BI Datasheet(HTML) 24 Page - Davicom Semiconductor, Inc.

Back Button DM9010BI Datasheet HTML 20Page - Davicom Semiconductor, Inc. DM9010BI Datasheet HTML 21Page - Davicom Semiconductor, Inc. DM9010BI Datasheet HTML 22Page - Davicom Semiconductor, Inc. DM9010BI Datasheet HTML 23Page - Davicom Semiconductor, Inc. DM9010BI Datasheet HTML 24Page - Davicom Semiconductor, Inc. DM9010BI Datasheet HTML 25Page - Davicom Semiconductor, Inc. DM9010BI Datasheet HTML 26Page - Davicom Semiconductor, Inc. DM9010BI Datasheet HTML 27Page - Davicom Semiconductor, Inc. DM9010BI Datasheet HTML 28Page - Davicom Semiconductor, Inc. Next Button
Zoom Inzoom in Zoom Outzoom out
 24 / 60 page
background image
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
Preliminary
24
Version: DM9010BI--DS-P01
January 12, 2010
6
ETS2
HPS0,RO
Early Transmit Status II (under run)
5
ETS1
HPS0,RO
Early Transmit Status I (under run)
4~2
RESERVED
000,RO
Reserved
1~0
ETT
HPS0,RW
Early Transmit Threshold
Start transmit when data write to TX FIFO reach the byte-count threshold
Bit-1 bit-0
threshold
----- ----
-------------
0
0
: 12.5%
0
1
: 25%
1
0
: 50%
1
1
: 75%
6.29 Transmit Check Sum Control Register (31H)
Bit
Name
Default
Description
7~3
RESERVED
0,RO
Reserved
2
UDPCSE
HPS0,RW
UDP Checksum Generation Enable
1
TCPCSE
HPS0,RW
TCP Checksum Generation Enable
0
IPCSE
HPS0,RW
IP Checksum Generation Enable
6.30 Receive Check Sum Control Status Register (32H)
Bit
Name
Default
Description
7
UDPS
HPS0,RO UDP Checksum Status
0: checksum OK, if UDP packet
6
TCPS
HPS0,RO TCP Checksum Status
0: checksum OK, if TCP packet
5
IPS
HPS0,RO IP Checksum Status
0: checksum OK, if IP packet
4
UDPP
HPS0,RO UDP Packet
3
TCPP
HPS0,RO TCP Packet
2
IPP
HPS0,RO IP Packet
1
RCSEN
HPS0,R
W
Receive Checksum Checking Enable
When set, the checksum status will store in packet first byte of status header.
0
DCSE
HPS0,R
W
Discard Checksum Error Packet
When set, if IP/TCP/UDP checksum field is error, this packet will be discarded.
6.31 External PHYceiver Address Register (33H)
Bit
Name
Default
Description
7
ADR_EN
HPS0,R
W
External PHY Address Enabled
When set in external MII mode, the external PHYceiver address is defined at bit
4~0.
6~5
Reserved
HPS0,RO Reserved
4~0
EPHYADR
HPS01,R
W
External PHY Address Bit 4~0
The PHY address in external MII mode.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com