LTC3577 datasheet(22/38 Pages) LINER

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LTC3675

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OPERATION

I2C Start and Stop Conditions

A bus master signals the beginning of communications

by transmitting a START condition. A START condition is

generated by transitioning SDA from HIGH to LOW while

SCL is HIGH. The master may transmit either the slave

write or the slave read address. Once data is written to the

LTC3675, the master may transmit a STOP condition which

commands the LTC3675 to act upon its new command

set. A STOP condition is sent by the master by transition-

ing SDA from LOW to HIGH while SCL is HIGH. The bus

is then free for communication with another I2C device.

I2C Byte Format

Each byte sent to or received from the LTC3675 must

be 8 bits long followed by an extra clock cycle for the

acknowledge bit. The data should be sent to the LTC3675

most signiﬁcant bit (MSB) ﬁrst.

I2C Acknowledge

The acknowledge signal is used for handshaking between

the master and the slave. When the LTC3675 is written

to (write address), it acknowledges its write address as

well as the subsequent two data bytes. When it is read

from (read address), the LTC3675 acknowledges its read

address only. The bus master should acknowledge receipt

of information from the LTC3675.

An acknowledge (active LOW) generated by the LTC3675

lets the master know that the latest byte of information was

received. The acknowledge related clock pulse is generated

by the master. The master releases the SDA line (HIGH)

during the acknowledge clock cycle. The LTC3675 pulls

down the SDA line during the write acknowledge clock

pulse so that it is a stable LOW during the HIGH period

of this clock pulse.

When the LTC3675 is read from, it releases the SDA line

so that the master may acknowledge receipt of the data.

Since the LTC3675 only transmits one byte of data during

a read cycle, a master not acknowledging the data sent

by the LTC3675 has no I2C speciﬁc consequence on the

operation of the I2C port.

I2C Slave Address

The LTC3675 responds to a 7-bit address which has been

factory programmed to b’0001001[R/WB]’. The LSB of

the address byte, known as the read/write bit, should be

0 when writing data to the LTC3675 and 1 when reading

data from it. Considering the address as an 8-bit word,

the write address is 12h and the read address is 13h. The

LTC3675 will acknowledge both its read and write address.

I2C Sub-Addressed Writing

The LTC3675 has twelve command registers for control

input. They are accessed by the I2C port via a sub-addressed

writing system.

A single write cycle of the LTC3675 consists of exactly three

bytes except when a clear interrupt command is written.

The ﬁrst byte is always the LTC3675’s write address. The

second byte represents the LTC3675’s sub-address. The

sub-address is a pointer which directs the subsequent

data byte within the LTC3675. The third byte consists of

the data to be written to the location pointed to by the

sub-address. The LTC3675 contains 11 control registers

which can be written to.

I2C Bus Write Operation

The master initiates communication with the LTC3675

with a START condition and the LTC3675’s write address.

If the address matches that of the LTC3675, the LTC3675

returns an acknowledge. The master should then deliver

the sub-address. Again the LTC3675 acknowledges and

the cycle is repeated for the data byte. The data byte is

transferred to an internal holding latch upon the return

of its acknowledge by the LTC3675. This procedure must

be repeated for each sub-address that requires new data.

After one or more cycles of [ADDRESS][SUB-ADDRESS]

[DATA], the master may terminate the communication

with a STOP condition. Multiple sub addresses may be

written to with a single address command using a [AD-

DRESS][SUB-ADDRESS][DATA][SUB-ADDRESS][DATA]

sequence. Alternatively, a REPEAT-START condition can be

initiated by the master and another chip on the I2C bus can

be addressed. This cycle can continue indeﬁnitely and the

LTC3675 will remember the last input of valid data that it

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