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LTC3577 Datasheet(PDF) 24 Page - Linear Technology |
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LTC3577 Datasheet(HTML) 24 Page - Linear Technology |
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24 / 38 page ![]() LTC3675 24 3675fa OPERATION data from the selected register. A STOP command is not required for the bus read operation. Immediately after writing data to a register, the contents of that register may be read back if the bus master issues a START condition followed by the LTC3675 read address. ERROR CONDITION REPORTING VIA RSTB AND IRQB PINS Error conditions are reported back via the IRQB and RSTB pins. After an error condition is detected, status data can be read back to a microprocessor via I2C to determine the exact nature of the error condition. Figure 4 is a simplified schematic showing the signal path for reporting errors via the RSTB and IRQB pins. All the switching regulators and the LED driver have an internal power good (PGOOD) signal. When the regulated output voltage of an enabled switcher rises above 93.5% of its programmed value, the PGOOD signal will transition high. When the regulated output voltage falls below 92.5% of its programmed value, the PGOOD signal is pulled low. If that PGOOD is not masked and stays low for greater than 50μs, then it pulls the RSTB and IRQB pins low, indicating to a microprocessor that an error condition has occurred. The 50μs filter time prevents the pins from being pulled low due to a transient. The LED driver has a PGOOD signal (PGOOD[7]) that is used to indicate output voltage status only when it is configured as a high voltage boost regulator. In all other operating modes, PGOOD[7] is disabled. An error condition that pulls the RSTB pin low is not latched. When the error condition goes away, the RSTB pin is released and is pulled high if no other error condi- tion exists. In addition to the PGOOD signals of the regulators, the IRQB pin also indicates the status of the overtemperature and undervoltage flags. The undervoltage and overtem- perature faults cannot be masked. A fault that causes the IRQB pin to be pulled low is latched. When the fault condition is cleared, the IRQB pin is still maintained in its low state. The user needs to clear the interrupt by using a CLRINT command. Figure 4. Simplified Schematic Showing RSTB and IRQB Signal Path 3675 F04 RSTB MASK REGISTER PGOOD COMPARATOR VOUT IRQB MASK REGISTER REGULATOR 92% OF PROGRAMMED VOUT OTHER UNMASKED PGOOD OUTPUTS UNMASKED PGOOD OUTPUTS UNMASKED ERROR EXTERNAL PULL-UP RESISTOR VIN AND1 AND2 OTHER UNMASKED ERRORS REAL TIME STATUS REGISTER LATCHED STATUS REGISTER SET CLR CLRINT EXTERNAL PULL-UP RESISTOR IRQB RSTB VIN |
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