LTC3577 datasheet(23/38 Pages) LINER

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LTC3675

3675fa

OPERATION

Table 1. Summary of I2C Sub-Addresses and Byte Formats. Bits A7, A6, A5, A4 of Sub-Address Need to Be 0 to Access Registers

SUB-ADDRESS

A7A6A5A4A3A2A1A0

OPER-

ATION ACTION

BYTE FORMAT

D7D6D5D4D3D2D1D0

DEFAULT

D7D6D5D4D3D2D1D0 COMMENTS

0000 0000 (00h)

Write

No Register

Selected

Used in the Clear Interrupt

Operation.

0000 0001 (01h)

Read/

Write

Buck1 Register

Enable, OUT_Hi-Z, Mode, Slow, DAC[3],

DAC[2], DAC[1], DAC[0]

01101111

0000 0010 (02h)

Read/

Write

Buck2 Register

Enable, OUT_Hi-Z, Mode, Slow, DAC[3],

DAC[2], DAC[1], DAC[0]

01101111

0000 0011 (03h)

Read/

Write

Buck3 Register

Enable, OUT_Hi-Z, Mode, Slow, DAC[3],

DAC[2], DAC[1], DAC[0]

01101111

0000 0100 (04h)

Read/

Write

Buck4 Register

Enable, OUT_Hi-Z, Mode, Slow, DAC[3],

DAC[2], DAC[1], DAC[0]

01101111

0000 0101 (05h)

Read/

Write

Boost Register

Enable, Unused, Mode, Slow, DAC[3],

DAC[2], DAC[1], DAC[0]

00001111

0000 0110 (06h)

Read/

Write

Buck-Boost

Enable, Unused, Mode, Slow, DAC[3],

DAC[2], DAC[1], DAC[0]

00001111

0000 0111 (07h)

Read/

Write

LED

Conﬁguration

Unused, Mode[1], Mode[0], Slow, 2XFS,

GRAD[2], GRAD[1], GRAD[0]

00001111

0000 1000 (08h)

Read/

Write

LED DAC

DAC[7], DAC[6], DAC[5], DAC[4], DAC[3],

DAC[2], DAC[1], DAC[0]

00000000

00000000 = LED Driver Disabled

11111111 = 25mA per String

0000 1001 (09h)

Read/

Write

UVOT Register

RESET_ALL, UV[2], UV[1], UV[0], UNUSED,

UNUSED, OT[1], OT[0]

00000000

0000 1010 (0Ah)

Read/

Write

RSTB Mask

UNUSED, PGOOD[7], PGOOD[6], PGOOD[5],

PGOOD[4], PGOOD[3], PGOOD[2], PGOOD[1]

11111111

Fault will pull RSTB low if the

corresponding bit is ‘1’

0000 1011 (0Bh)

Read/

Write

IRQB Mask

UNUSED, PGOOD[7], PGOOD[6], PGOOD[5],

PGOOD[4], PGOOD[3], PGOOD[2], PGOOD[1]

00000000

Fault will pull IRQB low if the

corresponding bit is ‘1’

0000 1100 (0Ch)

Read

Status Register

(Real Time)

UNUSED, UNUSED, PGOOD[6], PGOOD[5],

PGOOD[4], PGOOD[3], PGOOD[2], PGOOD[1]

Read Back

0000 1101 (0Dh)

Read

Status Register

(Latched)

UV, OT, PGOOD[6], PGOOD[5], PGOOD[4],

PGOOD[3], PGOOD[2], PGOOD[1]

Read Back

0000 1111 (0Fh)

Write

Clear Interrupt

Clears the Interrupt Bit,

Status Latches are Unlatched

received. Once all chips on the bus have been addressed

and sent valid data, a global STOP can be sent and the

LTC3675 will update its command latches with the data

that it had received.

It is important to understand that until a STOP signal is

transmitted, data written to the LTC3675 command reg-

isters is not acted on by the LTC3675. Only once a STOP

signal is issued is the data transferred to the command

latch and acted on. The one exception is when sub-address

0Fh is written to clear an interrupt. To clear an interrupt,

sub address OFh must be written, followed by sub address

00h. A complete clear interrupt cycle would have the fol-

lowing write sequence: 12h, 0Fh, STOP, 12h, 00h, STOP.

I2C Bus Read Operation

The LTC3675 has eleven command registers and two

status registers. The contents of any of these registers

may be read back via I2C.

To read the data of a register, that register’s sub-address

must be provided to the LTC3675. The bus master reads

the status of the LTC3675 with a START condition followed

by the LTC3675 write address followed by the ﬁrst data

byte (the sub-address of the register whose data needs

to be read) which is acknowledged by the LTC3675. After

receiving the acknowledge signal from the LTC3675 the

bus master initiates a new START condition followed by

the LTC3675 read address. The LTC3675 acknowledges

the read address and then returns a byte of read back

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