EDJ8232B5MB datasheet(60/142 Pages) ELPIDA

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EDJ8232B5MB

Data Sheet E1825E30 (Ver. 3.0)

CKE (input pin)

CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers.

Taking CKE low provides precharge power-down and self-refresh operation (all banks idle), or active power-down

(row active in any bank). CKE is asynchronous for self-refresh exit. After VREF has become stable during the

power-on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper

self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained high throughout read

and write accesses. Input buffers, excluding CK, /CK, ODT and CKE are disabled during power-down. Input buffers,

excluding CKE, are disabled during self-refresh.

DM0 to DM3 (input pins)

DM is an input mask signal for write data. Input data is masked when DM is sampled high coincident with that input

data during a write access. DM is sampled on both edges of DQS.

In this datasheet, DM represents DM0 to DM3.

DQ (input/output pins)

Bi-directional data bus.

DQS0 to DQS3, /DQS0 to /DQS3 (input/output pins)

Output with read data, input with write data. Edge-aligned with read data, center-aligned with write data.

The data strobe DQS is paired with differential signal /DQS to provide differential pair signaling to the system during

READs and WRITEs.

In this datasheet, DQS represents DQS0 to DQS3 and /DQS represents /DQS0 to /DQS3.

[DQS and DM Correspondence Table]

Part number

Organization

DQS

/DQS

Data mask

DQs

EDJ8232E5MB

 32 bits

DQS0

/DQS0

DM0

DQ0 to DQ7

DQS1

/DQS1

DM1

DQ8 to DQ15

DQS2

/DQS2

DM2

DQ16 to DQ23

DQS3

/DQS3

DM3

DQ24 to DQ31

/RESET (input pin)

/RESET is a CMOS rail to rail signal with DC high and low at 80% and 20% of VDD (1.20V for DC high and 0.30V

for DC low).

It is negative active signal (active low) and is referred to GND. There is no termination required on this signal. It will

be heavily loaded across multiple chips. /RESET is destructive to data contents.

ODT (input pin)

ODT (registered high) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is applied

to each DQ, DQS, /DQS, DM signal. The ODT pin will be ignored if the mode register (MR1) is programmed to

disable ODT.

ZQ0, ZQ1 (supply)

Reference pin for ZQ calibration.

VDD, VSS, VDDQ, VSSQ (power supply pins)

VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output

buffers.

VREFCA, VREFDQ (power supply pins)

Reference voltage

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