EDJ8232B5MB datasheet(63/142 Pages) ELPIDA

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EDJ8232B5MB

Data Sheet E1825E30 (Ver. 3.0)

Read Command [READ, RDS4, RDS8, READA, RDAS4, RDAS8]

The read command is used to initiate a burst read access to an active row. The values on the BA inputs select the

bank, and the address provided on column address inputs selects the starting column location. The value on input

A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be

precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent

accesses.

Write Command [WRIT, WRS4, WRS8, WRITA, WRAS4, WRAS8]

The write command is used to initiate a burst write access to an active row. The values on the BA inputs select the

bank, and the address provided on column address inputs selects the starting column location. The value on input

A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be

precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent

accesses.

Input data appearing on the DQ is written to the memory array subject to the DM input logic level

appearing coincident with the data. If a given DM signal is registered low, the corresponding data will be written to

memory; if the DM signal is registered high, the corresponding data inputs will be ignored, and a write will not be

executed to that byte/column location.

Precharge Command [PRE, PALL]

The precharge command is used to deactivate the open row in a particular bank or the open row in all banks. The

bank(s) will be available for a subsequent row access a specified time (tRP) after the precharge command is issued.

Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be

precharged, inputs BA select the bank.

Otherwise BA are treated as "Don't Care." Once a bank has been

precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that

bank. A precharge command will be treated as a NOP if there is no open row in that bank (idle state), or if the

previously open row is already in the process of precharging.

Auto precharge Command [READA, WRITA]

Before a new row in an active bank can be opened, the active bank must be precharged using either the precharge

command or the auto precharge function. When a read or a write command is given to the DDR3 SDRAM, the /CAS

timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at

the earliest possible moment during the burst read or write cycle. If A10 is low when the read or write command is

issued, then normal read or write burst operation is executed and the bank remains active at the completion of the

burst sequence. If A10 is high when the read or write command is issued, then the auto precharge function is

engaged. During auto precharge, a read command will execute as normal with the exception that the active bank

will begin to precharge on the rising edge which is (AL* + tRTP) cycles later from the read with auto precharge

command.

Auto precharge can also be implemented during write commands. The precharge operation engaged by the Auto

precharge command will not begin until the last data of the burst write sequence is properly stored in the memory

array.

This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent

upon /CAS latency) thus improving system performance for random data access. The tRAS lockout circuit internally

delays the Precharge operation until the array restore operation has been completed so that the auto precharge

command may be issued with any read or write command.

Note: AL (Additive Latency), refer to Posted /CAS description in the Register Definition section.

Auto-Refresh Command [REF]

Auto-refresh is used during normal operation of the DDR3 SDRAM and is analogous to /CAS-before-/RAS (CBR)

refresh in FPM/EDO DRAM. This command is nonpersistent, so it must be issued each time a refresh is required.

The addressing is generated by the internal refresh controller. This makes the address bits a "Don't Care" during an

auto-refresh command.

A maximum of eight auto-refresh commands can be posted to any given DDR3, meaning that the maximum absolute

interval between any auto-refresh command and the next auto-refresh command is 9

 tREFI. This maximum

absolute interval is to allow DDR3 output drivers and internal terminators to automatically recalibrate compensating

for voltage and temperature changes.

EDJ8232B5MB Datasheet(PDF) 63 Page - Elpida Memory

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