EDJ8232B5MB datasheet(76/142 Pages) ELPIDA

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EDJ8232B5MB

Data Sheet E1825E30 (Ver. 3.0)

DLL on/off switching procedure

DDR3 DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operations until

A0 bit set back to “0”.

DLL “on” to DLL “off” Procedure

To switch from DLL “on” to DLL “off” requires the frequency to be changed during self-refresh outlined in the

following procedure:

1. Starting from Idle state (all banks pre-charged, all timings fulfilled, and DRAMs On-die Termination resistors,

RTT, must be in high impedance state before MRS to MR1 to disable the DLL.)

2. Set MR1 Bit A0 to “1” to disable the DLL.

3. Wait tMOD.

4. Enter self-refresh mode; wait until (tCKSRE) satisfied.

5. Change frequency, in guidance with Input Clock Frequency Change during Precharge Power-Down section.

6. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs. After stable clock, wait tCKSRX

before issuing SRX command.

7. Starting with the self-refresh exit command, CKE must continuously be registered high until all tMOD timings from

any MRS command are satisfied. In addition, if any ODT features were enabled in the mode registers when self-

refresh mode was entered, the ODT signal must continuously be registered low until all tMOD timings from any

MRS command are satisfied. If both ODT features were disabled in the mode registers when self-refresh mode

was entered, ODT signal can be registered low or high.

8. Wait tXS, then set mode registers with appropriate values (especially an update of CL, CWL and WR may be

necessary. A ZQCL command may also be issued after tXS).

9. Wait for tMOD, then DRAM is ready for next command.

Tc Tc+1 Tc+2

Tf+2

Tf+1

Tg Tg+1

Command

CKE

ODT

/CK

MRS

SRE NOP

SRX

MRS

Valid

Change Frequency

tCKESR

tMOD

tCKSRE

tCKSRX

tXS

tMOD

DLL Switch Sequence from DLL-on to DLL-off

EDJ8232B5MB Datasheet(PDF) 76 Page - Elpida Memory

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