EDJ8232B5MB datasheet(18/142 Pages) ELPIDA

18 / 142 page

EDJ8232B5MB

Data Sheet E1825E30 (Ver. 3.0)

Single-Ended Requirements for Differential Signals

Each individual component of a differential signal (CK, DQS, /CK, /DQS) has also to comply with certain

requirements for single-ended signals.

CK and /CK have to reach VSEH min. / VSEL max. (approximately equal to the AC-levels (VIH(AC) / VIL(AC)) for

Address/command signals) in every half-cycle.

DQS, /DQS have to reach VSEH min./VSEL max. (approximately equal to the AC-levels (VIH(AC) / VIL(AC)) for DQ

signals) in every half-cycle preceding and following a valid transition.

Note that the applicable ac-levels for Address/command and DQ’s might be different per speed-bin etc. E.g. if VIH

150 (AC)/VIL 150 (AC) is used for Address/command signals, then these ac-levels apply also for the single ended

components of differential CK and /CK.

VSS or VSSQ

VDD or VDDQ

VSEL max.

VSEH min.

VSEH

VSEL

time

VDD/2 or VDDQ/2

CK or DQS

Single-Ended Requirement for Differential Signals.

Note that while Address/command and DQ signal requirements are with respect to VREF, the single-ended

components of differential signals have a requirement with respect to VDD / 2; this is nominally the same. The

transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended components

of differential signals the requirement to reach VSEL max, VSEH min has no bearing on timing, but adds a restriction

on the common mode characteristics of these signals.

EDJ8232B5MB Datasheet(PDF) 18 Page - Elpida Memory