EDJ8232B5MB datasheet(92/142 Pages) ELPIDA

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EDJ8232B5MB

Data Sheet E1825E30 (Ver. 3.0)

 DQS, /DQS crossing to Data Output

 tDQSQ; both rising/falling edges of DQS, no tAC defined

Notes: 1. BL8, RL = 5(AL = 0, CL = 5).

2. Dout n = data-out from column n.

3. NOP commands are shown for ease of illustration; other commands may be valid at these times.

4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] and A12 = 1 during READ command at T0.

5. Output timings are referenced to VDDQ/2, and DLL on for locking.

6. tDQSQ defines the skew between DQS, /DQS to data and does not define DQS, /DQS to clock.

7. Early data transitions may not always happen at the same DQ.

Data transitions of a DQ can vary(either early or late) within a busy.

VIH or VIL

READ

/CK

T10

Command*3

DQS, /DQS

DQ*2

(Last data valid)

NOP

Address*4

Bank

Coln

DQ*2

(First data no longer valid)

All DQS collectively

tRPST

RL = AL + CL

tQH

tRPRE

tDQSQ(max.)

Dout

n+1

Dout

n+2

Dout

n+3

Dout

n+4

Dout

n+5

Dout

n+6

Dout

n+7

Data valid

Dout

n+1

Dout

n+2

Dout

n+3

Dout

n+4

Dout

n+5

Dout

n+6

Dout

n+7

Dout

n+1

Dout

n+2

Dout

n+3

Dout

n+4

Dout

n+5

Dout

n+6

Dout

n+7

tLZ(DQ)(min.)

tLZ(DQ)(max.)

tHZ(DQ)(max.)

tDQSQ(max.)

DDR3 Data Strobe to Data Relationship

EDJ8232B5MB Datasheet(PDF) 92 Page - Elpida Memory

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