DMD_D(1:0)

DMD_SCTRL

DMD_TRC

DMD_LOADB

DMD_DCLK

tp_su

tp _h

DMD_SAC_CLK

DMD_SAC_BUS

DMD_DAD_OEZ

DMD_DAD_BUS

DMD_DAD_STRB

tclk_skew

tp_wh

tp_wl

tp_d2_skew

tp_d1_skew

DLPC100

DLPS019B – DECEMBER 2009 – REVISED DECEMBER 2010

www.ti.com

DMD Interface

The DLPC100 ASIC DMD interface consists of a 60.0 MHz (nominal) DDR output-only interface with LVCMOS

signaling.

DMD INTERFACE TIMING REQUIREMENTS

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Clock frequency, DMD_DCLK & DMD_SAC_CLK

60.05

MHz

Clock period, DMD_DCLK & DMD_SAC_CLK

50% reference points

16.5

ns

Clock jitter, DMD_DCLK & DMD_SAC_CLK

200

ps

Pulse width low, DMD_DCLK & DMD_SAC_CLK

50% reference points

7.5

ns

Pulse width high, DMD_DCLK & DMD_SAC_CLK

50% reference points

7.5

ns

20% to 80% reference

0.3

2.0

ns

Transition time – all signals

points

Output setup time – DMD_D(14:0), DMD_SCTRL,

1.5

ns

tp_su

DMD_LOADB & DMD_TRC relative to both rising and

50% reference points

falling edges of DMD_DCLK

Output hold time – DMD_D(14:0), DMD_SCTRL,

1.5

ns

DMD_LOADB & DMD_TRC signals relative to both rising

50% reference points

and falling edges of DMD_DCLK DMD

Data skew – DMD_D(14:0), DMD_SCTRL, DMD_LOADB &

0.20

ns

50% reference points

DMD_TRC signals relative to each other

Clock skew – DMD_DCLK & DMD_SAC_CLK relative to

0.20

ns

50% reference points

each other DAD/ SAC

Data Skew - DMD_SAC_BUS, DMD_DAD_OEZ,

0.20

ns

50% reference points

DMD_SAC_CLK

(1)

This range include the 200 ppm of the external oscillator

Figure 10. DMD I/F Timing

16

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