MEM_CLK

tCH

tCL

MEM_DQ(15:0)

MEM_xDQM

MEM_RAS \

MEM_CAS \

MEM_WE\

MEM_CS\

MEM_CKE

mSDR Memory Write Data Timing

tCYCLE

tCMS

MEM_A(11 :0)

MEM _BA(11 :0)

tCMH

tAS

tAH

tDS

tDH

DLPC100

www.ti.com

DLPS019B – DECEMBER 2009 – REVISED DECEMBER 2010

Mobile SDR Memory Interface

The DLPC100 Controller Mobile SDR Memory interface consists of a 16-bit wide, mobile SDR interface (i.e.

LVCMOS signaling) operated at 100.0 MHz (nominal).

MOBILE SDR MEMORY INTERFACE TIMING REQUIREMENTS

PARAMETER

MIN

MAX

UNIT

Cycle time reference

10

ns

3

ns

3

ns

Command setup

1.5

ns

Command hold

1

ns

Address setup

1.5

ns

Address hold

1

ns

Write data setup

2.5

ns

Write data hold

1

ns

Read data access time

8

ns

Read data hold time

2.5

ns

Read data low impedance time

1

ns

Read data high impedance time

8

ns

(1)

DQS pulse width requirements to the memory.

Figure 11. Mobile SDR Memory I/F Write Timing

Copyright © 2009–2010, Texas Instruments Incorporated

Submit Documentation Feedback

17

Product Folder Link(s): DLPC100