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DLPC100ZCT Datasheet(PDF) 7 Page - Texas Instruments |
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DLPC100ZCT Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 25 page  DLPC100 www.ti.com DLPS019B – DECEMBER 2009 – REVISED DECEMBER 2010 TERMINAL FUNCTIONS (continued) TERMINAL I/O CLOCK DESCRIPTION TYPE SYSTEM NAME NO. DMD_TRC T10 O3 DMD_CLK DMD data toggle rate control DMD_A0 T11 O3 DMD_CLK DMD reset address 0 DMD_A1 T14 O3 DMD_CLK DMD reset address 1 DMD_A2 T12 O3 DMD_CLK DMD reset address 2 DMD_SEL0 K16 O3 DMD_CLK DMD reset select 0 DMD_SEL1 T15 O3 DMD_CLK DMD reset select 1 DMD_MODE R10 O3 DMD_CLK DMD reset mode DMD_STROBE T13 O3 DMD_CLK DMD reset strobe DMD_SACBUS L16 O3 DMD_CLK DMD serial bus data DMD_SACCLK K15 O3 DMD_CLK DMD serial bus clock DMD_OEZ R14 O3 DMD_CLK DMD reset output enable DMD_PWR_EN G5 O3 N/A DMD power regulator enable RESERVED H16 O3 N/A Pin reserved for future use RESERVED H15 I4 N/A Not used. Pin reserved for future use. SDRAM Interface MEM_A0 D12 O2 MEM_CLK Multiplexed row and column address 0 for the SDRAM MEM_A1 B12 O2 MEM_CLK Multiplexed row and column address 1 for the SDRAM MEM_A2 B14 O2 MEM_CLK Multiplexed row and column address 2 for the SDRAM MEM_A3 C14 O2 MEM_CLK Multiplexed row and column address 3 for the SDRAM MEM_A4 D14 O2 MEM_CLK Multiplexed row and column address 4 for the SDRAM MEM_A5 A15 O2 MEM_CLK Multiplexed row and column address 5 for the SDRAM MEM_A6 A13 O2 MEM_CLK Multiplexed row and column address 6 for the SDRAM MEM_A7 B13 O2 MEM_CLK Multiplexed row and column address 7 for the SDRAM MEM_A8 A14 O2 MEM_CLK Multiplexed row and column address 8 for the SDRAM MEM_A9 B3 O2 MEM_CLK Multiplexed row and column address 9 for the SDRAM MEM_A10 A12 O2 MEM_CLK Multiplexed row and column address 10 for the SDRAM MEM_A11 D11 O2 MEM_CLK Multiplexed row and column address 11 for the SDRAM MEM_BA0 B11 O2 MEM_CLK Bank select for the SDRAM MEM_BA1 A11 O2 MEM_CLK Bank select for the SDRAM MEM_RAS C9 O2 MEM_CLK Row address strobe. Active low. MEM_CAS D9 O2 MEM_CLK Column address strobe. Active low. MEM_CKE E9 O2 MEM_CLK Clock enable. Active high. MEM_CS B10 O2 MEM_CLK Chip select. Active low. MEM_HDQM A10 O2 MEM_CLK Data mask high byte. MEM_LDQM D8 O2 MEM_CLK Data mask low byte MEM_WE F8 O2 MEM_CLK Write enable. Active low. MEM_CLK F9 O2 N/A Memory clock. Generated by internal PLL. 100 MHz MEM_DQ0 A3 B3 MEM_CLK Bidirectional data 0 for the SDRAM MEM_DQ1 B4 B3 MEM_CLK Bidirectional data 1 for the SDRAM MEM_DQ2 A5 B3 MEM_CLK Bidirectional data 2 for the SDRAM MEM_DQ3 A6 B3 MEM_CLK Bidirectional data 3 for the SDRAM MEM_DQ4 B6 B3 MEM_CLK Bidirectional data 4 for the SDRAM MEM_DQ5 E6 B3 MEM_CLK Bidirectional data 5 for the SDRAM MEM_DQ6 A7 B3 MEM_CLK Bidirectional data 6 for the SDRAM MEM_DQ7 C8 B3 MEM_CLK Bidirectional data 7 for the SDRAM MEM_DQ8 E8 B3 MEM_CLK Bidirectional data 8 for the SDRAM Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): DLPC100 |
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