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DLPC100ZCT Datasheet(PDF) 15 Page - Texas Instruments

Part # DLPC100ZCT
Description  DLP짰 Digital Controller for the DLP1700 DMD
PDF  25 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DLPC100ZCT Datasheet(HTML) 15 Page - Texas Instruments

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SPI_CLK
SPI_DATA
tp_su
tp_h
tp_wh
tp_wl
tp_clkper
DLPC100
www.ti.com
DLPS019B – DECEMBER 2009 – REVISED DECEMBER 2010
I
2C Bus Transactions
Data is exchanged between the master and the DLPC100 through write and read commands.
Writes
Data is transmitted to the DLPC100 by sending the device address and setting the least-significant bit to a logic
0. The data bytes are sent after the address and determines which register receives the data that follows the
address byte. Data is clocked into the register on the rising edge of the ACK clock pulse. .
Reads
The bus master first must send the DLPC100 address with the least-significant bit set to a logic 0. The read
address byte is sent after the device address and read command (x15) and the read address determines which
register is accessed. After a restart, the device address is sent again, but this time, the least-significant bit is set
to a logic 1. Data from the register defined by the read address byte then is sent by the DLPC100. See
Programmers guide for a full description of the register read/write protocol and available registers.
Flash Memory Interface
The DLPC100 controller flash memory interface consists of a SPI flash serial interface at 33.3 MHz (nominal).
FLASH INTERFACE TIMING REQUIREMENTS
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
fclock
Clock frequency, SPI_CLK
See (1)
33.3266
33.34
MHz
tp_clkper
Clock period, SPI_CLK
50% reference points
29.994
30.006
ns
tp_clkjit
Clock jitter, SPI_CLK
Max fclock
200
ps
tp_wh
Pulse width low, SPI_CLK
50% reference points
10
ns
tp_wl
Pulse width high, SPI_CLK
50% reference points
10
ns
tt
Transition time – all signals
20% to 80% reference points
0.2
4
ns
Setup Time – SPI_DIN valid before SPI_CLK rising
10
ns
tp_su
50% reference points
edge
Hold Time – SPI_DIN valid after SPI_CLK rising
0
ns
tp_h
50% reference points
edge
SPI_CLK clock low to output valid time – SPI_DOUT
1
ns
tp_clqv
50% reference points
& SPI_CSZ
SPI_CLK clock low output hold time – SPI_DOUT &
-1
ns
tp_clqx
50% reference points
SPI_CSZ
(1)
This range include the 200 ppm of the external oscillator
Figure 9. Flash Memory Interface Timing
Copyright © 2009–2010, Texas Instruments Incorporated
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15
Product Folder Link(s): DLPC100



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