TAS5721 datasheet(44/71 Pages) TI1

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TAS5721

SLOS739 – JULY 2012

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DETAILED DESCRIPTION AND THEORY OF OPERATION

POWER SUPPLY

To facilitate system design, the TAS5721 needs only a 3.3-V supply in addition to the PVDD power-stage supply.

The required sequencing of the power supplies is shown in the Recommended Use Model section. An internal

voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all circuitry requiring a

floating voltage supply, for example, the high-side gate drive, is accommodated by built-in bootstrap circuitry

requiring only a few external capacitors.

In order to provide good electrical and acoustical characteristics, the PWM signal path for the output stage is

designed as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins

(BSTRPx) and power-stage supply pins (PVDD). The gate drive voltage (GVDD_REG) is derived from the PVDD

voltage. Special attention should be paid to placing all decoupling capacitors as close to their associated pins as

possible. In general, inductance between the power-supply pins and decoupling capacitors must be avoided.

For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin

(BSTRPx) to the power-stage output pin (SPK_OUTx). When the power-stage output is low, the bootstrap

capacitor is charged through an internal diode connected between the gate-drive regulator output pin (GVDD_X)

and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the

output potential and thus provides a suitable voltage supply for the high-side gate driver. As shown in the Typical

Application Circuits section, it is recommended to use ceramic capacitors, for the bootstrap supply pins. These

capacitors ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power

stage FET (LDMOS) fully turned on during the remaining part of the PWM cycle.

Special attention should be paid to the power-stage power supply; this includes component selection, PCB

placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD). For

optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD pin is

decoupled with a ceramic capacitor placed as close as possible to each supply pin, as shown in the Typical

Application Circuits section.

The TAS5721 is fully protected against erroneous power-stage turn-on due to parasitic gate charging.

2C Address Selection and Fault Output

ADR/FAULT is an input pin during power up. It can be pulled HIGH or LOW through a resistor as shown in the

Typical Application Circuits section in order to set the I2C address. Pulling this pin HIGH through the resistor

results in setting the I2C 7-bit address to 0011011 (0x36), and pulling it LOW through the resistor results in

setting the address to 0011010 (0x34).

During power up, the address of the device is latched in, freeing up the ADR/FAULT pin to be used as a fault

notification output. When configured as a fault output, the pin will go low when a fault occurs and will return to it's

default state when register 0x02 is cleared. The device will pull the fault pin low for over-current, over-

temperature, over-voltage lock-out, and under-voltage lock-out.

DEVICE PROTECTION SYSTEM

Overcurrent (OC) Protection With Current Limiting

The device has independent, fast reacting current detectors on all high-side and low-side power-stage FETs. The

detector outputs are closely monitored by a protection system. If the high-current condition situation persists, a

protection system triggers a latching shutdown, resulting in the power stage being set in the high-impedance (Hi-

Z) state. After the power stage enters into this state, the power stage will attempt to restart after a period of time

defined in register 0x1C. If the high-current condition persists, the device will begin the shutdown and retry

sequence again. The device will return to normal operation once the fault condition is removed. Current limiting

and overcurrent protection are not independent for half-bridges. That is, if the bridge-tied load between half-

bridges A and B causes an overcurrent fault, half-bridges A, B, C, and D are shut down.

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