TAS5721 datasheet(51/71 Pages) TI1

51 / 71 page

7-BitSlave Address

8-BitRegister Address(N)

8-BitRegisterDataFor

Address(N)

Start

Stop

SDA

SCL

8-BitRegisterDataFor

Address(N)

T0035-01

TAS5721

www.ti.com

SLOS739 – JULY 2012

2C SERIAL CONTROL INTERFACE

The TAS5721 DAP has a bidirectional inter-integrated circuit (I2C) interface that is compatible with the I2C bus

protocol and supports both 100-kHz and 400-kHz data transfer rates for single and multiple byte write and read

operations. This is a slave only device that does not support a multimaster bus environment or wait state

insertion. The control interface is used to program the registers of the device and to read device status.

The DAP supports the standard-mode I2C bus operation (100 kHz maximum) and the fast I2C bus operation

(400 kHz maximum). The DAP performs all I2C operations without I2C wait cycles.

General I2C Operation

The I2C bus employs two signals to communicate between integrated circuits in a system: (data) SDA and (clock)

SCL. Data is transferred on the bus serially one bit at a time. The address and data can be transferred in byte (8-

bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is

acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master

device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.

The bus uses transitions on the data pin (SDA) while the clock is high to indicate start and stop conditions. A

high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data bit

transitions must occur within the low time of the clock period. These conditions are shown in Figure 61. The

master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another

device and then waits for an acknowledge condition. The TAS5721 holds SDA low during the acknowledge clock

period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence.

Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the

same signals through a bidirectional bus using a wired-AND connection. An external pullup resistor must be used

for the SDA and SCL signals to set the high level for the bus.

Figure 61. Typical I2C Sequence

There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last

word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is

shown in Figure 61.

Pin ADR/FAULT defines the I2C device address. An external 15-k

Ω pull down on this pin gives a device address

of 0x34 and a 15-k

Ω pull up gives a device address of 0x36. The 7-bit address is 0011011 (0x36) or 0011010

(0x34).

I2C Device Address Change Procedure

•

Write to device address change enable register, 0xF8 with a value of 0xF9 A5 A5 A5.

•

Write to device register 0xF9 with a value of 0x0000 00XX, where XX is the new address.

•

Any writes after that should use the new device address XX.

Single- and Multiple-Byte Transfers

The serial control interface supports both single-byte and multiple-byte read/write operations for subaddresses

0x00 to 0x1F. However, for the subaddresses 0x20 to 0xFF, the serial control interface supports only multiple-

byte read/write operations (in multiples of 4 bytes).

Submit Documentation Feedback

Product Folder Links: TAS5721

TAS5721 Datasheet(PDF) 51 Page - Texas Instruments

TAS5721 Datasheet(HTML) 51 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71

Datasheet Download

Link URL