TAS5721 datasheet(45/71 Pages) TI1

45 / 71 page

TAS5721

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SLOS739 – JULY 2012

Overtemperature Protection

The TAS5721 has an overtemperature-protection system. If the device junction temperature exceeds 150°C

(nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-

impedance (Hi-Z) state and ADR/FAULT, if configured as an output, being asserted low. The TAS5721 recovers

automatically once the temperature drops approximately 30 °C.

Undervoltage Protection (UVP) and Power-On Reset (POR)

The UVP and POR circuits of the TAS5721 fully protect the device in any power-up/down and brownout situation.

While powering up, the POR circuit ensures that all circuits are fully operational when the PVDD and AVDD

supply voltages reach 4.1 V and 2.7 V, respectively. Although PVDD and AVDD are independently monitored, a

supply voltage drop below the UVP threshold on AVDD or on either PVDD pin results in all half-bridge outputs

immediately being set in the high-impedance (Hi-Z) state and ADR/FAULT, if configured as an output, being

asserted low.

CLOCK, AUTO DETECTION, AND PLL

The TAS5721 is a slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP)

supports all the sample rates and MCLK rates that are defined in the Clock Control Register section.

The TAS5721 checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only supports a 1 ×

fS LRCLK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The clock section

uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce the

internal clock (DCLK) running at 512 times the PWM switching frequency.

The DAP can autodetect and set the internal clock control logic to the appropriate settings for all supported clock

rates as defined in the clock control register.

TAS5721 has robust clock error handling that uses the built-in trimmed oscillator clock to quickly detect

changes/errors. Once the system detects a clock change/error, it will mute the audio (through a single step mute)

and then force PLL to operate in a reduced capacity using the internal oscillator as a reference clock. Once the

clocks are stable, the system will auto detect the new rate and revert to normal operation. During this process,

the default volume will be restored in a single step (also called hard unmute) by default. If desired, the unmuting

process can be programmed to ramp back slowly (also called soft unmute) as defined in volume register (0x0E).

SERIAL DATA INTERFACE

Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5721 DAP accepts serial data in

16-, 20-, or 24-bit left-justified, right-justified, and I2S serial data formats.

PWM Section

The TAS5721 DAP device uses noise-shaping and sophisticated non-linear correction algorithms to achieve high

power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to

increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from the DAP

and outputs up to three PWM audio output channels.

The PWM modulation block has individual channel dc blocking filters that can be enabled and disabled. The filter

cutoff frequency is less than 1 Hz. Individual channel de-emphasis filters for 44.1- and 48-kHz are included and

can be enabled and disabled.

Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%. It is important to note

that for any applications with PVDD greater than 18 V, the maximum modulation index must be set to 93.8%.

SERIAL INTERFACE CONTROL AND TIMING

The I2S mode is set by writing to register 0x04.

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