TAS5721 datasheet(54/71 Pages) TI1

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CH1_audio

CH2_audio

PWM1

PWM2

OFF3

OFF4

B0488-01

D (Off)

B (Off)

C (R–)

–

A (L+)

CH1_audio

PWM1

PWM3

OFF2

OFF4

B0488-02

–

D (Off)

B (Off)

C (L–)

A (L+)

CH1_audio

CH3_audio

CH2_audio

PWM1

PWM2

PWM3

PWM4

B0487-04

D (S )

–

B (

)

R–

C (S+)

A (L+)

CH1_audio

CH3_audio

CH2_audio

PWM1

PWM2

PWM3

PWM4

B0487-03

D (S )

–

B (

)

R–

C (S+)

A (L+)

CH1_audio

CH2_audio

PWM1

PWM2

PWM3

PWM4

B0487-02

D (

)

R–

B (L )

–

C (R+)

A (L+)

CH1_audio

CH2_audio

PWM1

PWM2

PWM3

PWM4

B0487-01

D (

)

R–

B (L )

–

C (R+)

A (L+)

TAS5721

SLOS739 – JULY 2012

www.ti.com

Table 21. Output Configuration Quick Reference

Output

Modulation Mode

Block Diagram

Configuration

0x20[23] = 0

0x20[19] = 0

0x20[15:8] = 0x77

AD for Both Outputs

0x05[7] = 0

0x05[2] = 0

0x25[23:8] = 0x0213

0x1A[7:0] = 0x0F

2.0 (Stereo BTL)

0x20[23] = 1

0x20[19] = 1

0x20[15:8] = 0x77

BD for Both Outputs

0x05[7] = 0

0x05[2] = 0

0x25[23:8] = 0x0213

0x1A[7:0] = 0x0A

0x20[23] = 0

0x20[19] = 0

Single Device 2.1

0x20[3] = 0

(Stereo Single

0x05[7] = 1

Ended + Mono

AD for Both SE Outputs

0x05[2] = 1

BTL)

AD for Single BTL

0x25[23:8] = 0x0132

Note: In these

Output

0x1A[7:0] = 0x95

described

0x20[7:4] = 0x7

configurations, the

0x21[8] = 0

polarity of the

0x20[25] = 1

signal being sent to

SPK_OUTB is

0x20[23] = 0

inverted. For this

0x20[19] = 0

reason, care

0x20[3] = 1

should be taken to

0x05[7] = 1

AD for both SE Outputs

ensure that the

0x05[2] = 1

BD for Single BTL

speakers are

0x25[23:8] = 0x0132

Output

connected as

0x1A[7:0] = 0x95

shown in the block

0x20[7:4] = 0x7

diagram.

0x21[8] = 0

0x20[25] = 1

0x05[7] = 0

0x05[5] = 0

0x05[2] = 0

0x19[7:0] = 0x3A

0x1A[7:0] = 0x0F

0x20[23] = 0

0x20[15:12] = 0x7

0x25[23:8] = 0x0123

1.0 Mono PBTL

0x05[7] = 0

0x05[5] = 0

0x05[2] = 0

0x19[7:0] = 0x3A

0x1A[7:0] = 0x0A

0x20[23] = 1

0x20[15:12] = 0x7

0x25[23:8] = 0x0123

2.1-Mode Support

The TAS5721 uses a special mid-Z ramp sequence to reduce click and pop in SE-mode and 2.1-mode operation.

To enable the mid-Z ramp, register 0x05 bit D7 must be set to 1. To enable 2.1 mode, register 0x05 bit D2 must

be set to 1. The SSTIMER pin should be left floating in this mode.

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