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TAS5721 Datasheet(PDF) 10 Page - Texas Instruments |
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TAS5721 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 71 page ![]() SCL SDA t h2 t (buf) t su2 t su3 Start Condition Stop Condition T0028-01 SCL SDA t w(H) t w(L) t r t f t su1 t h1 T0027-01 TAS5721 SLOS739 – JULY 2012 www.ti.com I 2C Serial Control Port Requirements and Specifications PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, external components per Typical Application Circuit diagrams, and in accordance with recommended operating conditions (unless otherwise specified). PARAMETER TEST CONDITIONS MIN MAX UNIT fSCL Frequency, SCL No wait states 400 kHz tw(H) Pulse duration, SCL high 0.6 μs tw(L) Pulse duration, SCL low 1.3 μs tr Rise time, SCL and SDA 300 ns tf Fall time, SCL and SDA 300 ns tsu1 Setup time, SDA to SCL 100 ns th1 Hold time, SCL to SDA 0 ns t(buf) Bus free time between stop and start conditions 1.3 μs tsu2 Setup time, SCL to start condition 0.6 μs th2 Hold time, start condition to SCL 0.6 μs tsu3 Setup time, SCL to stop condition 0.6 μs CL Load capacitance for each bus line 400 pF Figure 6. SCL and SDA Timing Figure 7. Start and Stop Conditions Timing 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 |
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