TC246

SOCS096 – JULY 2010

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DETAILED DESCRIPTION

The TC246 consists of five basic functional blocks: The image-sensing area, the image-storage area, the serial

register, the charge multiplier, and the charge detection node with buffer amplifier. The location of each of these

blocks is identified in the functional block diagram.

Image Sensing and Storage areas

As light enters the silicon in the image-sensing area, electrons are generated and collected in potential wells of

the pixels. Color is accomplished by on-chip color mosaic filter. (see the sensor topology diagram for a mapping

of the color filter) Applying a suitable DC bias to the antiblooming drain provides blooming protection. The

electrons that exceed a specific level, determined by the ODB bias, are drained away from the pixels. After the

integration cycle is completed by applying a PD-cell readout pulse to IAG2, charge is transferred from the PD-cell

into the V-cell and then quickly transferred into the storage cell where it waits for readout. TC246CYM-B0

enables 2 lines to sum together to implement the pseudo-interlace scan.

Additionally, 4 dark lines, located between the image sensing area and the image-storage area, were added to

the array for isolation.

Advanced Lateral Overflow Drain

Each pixel is constructed with the advanced lateral overflow drain structure. By varying the DC bias of the

anti-blooming drain it is possible to control the blooming protection level and trade it for well capacity.

Electronic Exposure Control

Precise exposure control timing on a frame-by-frame basis is possible. The integration time can be arbitrarily

shortened from its nominal length by clearing residual charge from the PD-cell. To do this, apply a PD-cell clear

pulse to IAG2, which marks the beginning of integration.

Serial Register and Charge Multiplier

The serial register of TC246 image sensor consists of only poly-silicon gates. It operates at high speed, being

clocked from 0 V to 8 V. This allows the sensor to work at 30 frames/s. The serial register is used for transporting

charge stored in the pixels of the memory lines to the output amplifier. The TC246 device has a serial register

with twice the standard length. The first half has a conventional design that interfaces with the memory as it

would in any other CCD sensor. The second half, however, is unique and includes 400 charge multiplication

stages with a number of dummy pixels that are needed to transport charge between the active register blocks

and the output amplifier. Charge is multiplied as it progresses from stage to stage in the multiplier toward the

charge detection node. The charge multiplication level depends on the amplitude of the multiplication pulses

(approximately 15 V to 22 V) applied to the multiplication gate. Due to the double length of the register, first two

lines in each field or frame scan do not contain valid data and should be discarded.

Charge Detection Node and Buffer Amplifier

The last element of the charge detection and readout chain is the charge detection node with the buffer amplifier.

The charge detection node is using a standard Floating Diffusion (FD) concept followed by an on-chip,

dual-stage, source-follower buffer. Applying a pulse to the RST pin resets the detection node. Pixel charge

summing function can be easily implemented by skipping the RST pulses. To achieve the ultimate sensor

performance it is necessary to eliminate kTC noise. This is typically accomplished by using CDS (correlated

double sampling) processing techniques. IMPACTRON devices have the potential for detecting single electrons

(photons) when cooled sufficiently.

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