WM8224 datasheet(42/50 Pages) WOLFSON

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WM8224

Production Data

PD, Rev 4.1, June 2012

The following table describes the function of each of the control bits shown in Table 15.

NAME

BIT

NAME(S)

DEFAULT

DESCRIPTION

R0 (00h)

Device ID

7:0

10000010

Read only register. Reading from this register returns the

first 2 digits of device part number.

R1 (01h)

Setup

Global Enable

0 = complete power down,

1 = fully active (individual blocks can be disabled using

individual powerdown bits – see setup register 5).

CDS

Select correlated double sampling mode:

0 = non-CDS mode,

1 = CDS mode.

MONO

Sampling mode select

0 = other mode (2 or 3-channel)

1 = Monochrome (1-channel) mode. Input channel

selected by CHAN[1:0] register bits, unused channel is

powered down.

TWOCHAN and MONO should not be set concurrently.

TWOCHAN

Sampling mode select

0 = other mode (1 or 3-channel)

1 = 2-channel mode.

TWOCHAN and MONO should not be set concurrently.

5:4

PGAFS[1:0]

Offsets PGA output to optimise the ADC range for different

polarity sensor output signals. Zero differential PGA input

signal gives:

0x = Zero output from the PGA (Output code=511)

10 = Full-scale positive output (OP=1023) – use for

negative going video.

NB, Set INVOP=1 if zero differential input

should give a zero output code with negative

going video.

11 = Full-scale negative output (OP=0) - use for positive

going video

7:6

ACLKDIV[1:0]

Reduces the internal clock frequency to allow analogue

circuitry to run at a slower rate when daisy chaining

devices.

00 – no divide

01 – divide MCLK by 2 internally

10 – divide MCLK by 3 internally

11 – not valid

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