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WM8224 Datasheet(PDF) 46 Page - Wolfson Microelectronics plc |
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WM8224 Datasheet(HTML) 46 Page - Wolfson Microelectronics plc |
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46 / 50 page  WM8224 Production Data w PD, Rev 4.1, June 2012 46 REGISTER REGISTER NAME BIT NO BIT NAME(S) DEFAULT DESCRIPTION R37 (25h) PGA Gain LSB (Green) 0 PGAG[0] 0 This register bit forms the LSB of the green channel PGA gain code. PGA gain is determined by combining this register bit and the 8 MSBs contained in register address 29 hex. R38 (26h) PGA Gain LSB (Blue) 0 PGAB[0] 0 This register bit forms the LSB of the blue channel PGA gain code. PGA gain is determined by combining this register bit and the 8 MSBs contained in register address 2A hex. R39 (27h) PGA Gain LSB (RGB) 0 PGARGB[0] - Writing a value to this location causes red, green and blue PGA LSB gain values to be overwritten by the new value. R40 (28h) PGA gain MSBs (Red) 7:0 PGAR[8:1] 00001100 Bits 8 to 1 of red PGA gain. Combined with red LSB register bit to form complete PGA gain code. This determines the gain of the red channel PGA according to the equation: Red channel PGA gain (V/V) = 0.66 + PGAR[8:0]x7.34/511 R41 (29h) PGA gain MSBs (Green) 7:0 PGAG[8:1] 00001100 Bits 8 to 1 of green PGA gain. Combined with green LSB register bit to form complete PGA gain code. This determines the gain of the green channel PGA according to the equation: Green channel PGA gain (V/V) = 0.66 + PGAG[8:0]x7.34/511 R42 (2Ah) PGA gain MSBs (Blue) 7:0 PGAB[8:1] 00001100 Bits 8 to 1 of blue PGA gain. Combined with blue LSB register bit to form complete PGA gain code. This determines the gain of the blue channel PGA according to the equation: Blue channel PGA gain (V/V) = 0.66 + PGAB[8:0]x7.34/511 R43 (2Bh) PGA gain MSBs (RGB) 7:0 PGARGB[8:1] - A write to this register location causes the red, green and blue PGA MSB gain registers to be overwritten by the new value. R44 (2Ch) BLC Control 5 6:0 BLC_DEL [6:0] 0000000 Determines the number of pixels (from the start of a line) to delay the start of a BLC operation. 7 LINE_DEL [8] 0 MSB of the number of lines from the start of a frame to delay the start of a BLC operation. R45 (2Dh) BLC Control 6 7:0 LINE_DEL [7:0] 00000000 LSBs of the number of lines from the start of a frame to delay the start of a BLC operation. Table 16 Register Control Bits |
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