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WM8224 Datasheet(PDF) 14 Page - Wolfson Microelectronics plc |
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WM8224 Datasheet(HTML) 14 Page - Wolfson Microelectronics plc |
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14 / 50 page ![]() WM8224 Production Data w PD, Rev 4.1, June 2012 14 Test Conditions AVDD = DVDD = 3.3V, AGND = DGND = 0V, TA = 25C. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS MCLK period, ACLKDIV=00 (default) tPER 12 or 16 bit 25 ns tPER 8 or 10 bit 16.67 ns MCLK high period tMCLKH 0.5 MCLK periods MCLK low period tMCLKL 0.5 MCLK periods MCLK Duty Cycle 45:55 55:45 % RSMP pulse high time tRSD 3 ns VSMP pulse high time tVSD 2 ns RSMP falling to VSMP rising time tRSFVSR 0 ns MCLK rising to VSMP rising time tMRVSR 3 ns MCLK falling to VSMP falling time tMFVSF 7 ns VSMP falling to MCLK rising time tVSFMR 0 ns 1 st MCLK falling edge after VSMP falling to RSMP falling time tMF1RSF 7 ns 3-channel mode pixel period tPR3 3 MCLK periods 2-channel mode pixel period tPR2 2 MCLK periods 1-channel mode pixel period tPR1 1 MCLK periods Output latency. From 1 st rising edge of MCLK after VSMP falling to data output LAT OPDEL[3:0]=0000, ACLKDIV=00 7 MCLK periods Notes: 1. Parameters are measured at 50% of the rising/falling edge. OUTPUT DATA TIMING OEB OP Hi-Z tPZE Hi-Z tPEZ Figure 7 Output Enable/Disable Timing from OEB Pin MCLK OP Hi-Z t PD t PAEZ Hi-Z t PAZE Figure 8 Output Enable/Disable Timing with AUTOZ=1 |
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