WM8310 datasheet(62/291 Pages) WOLFSON

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WM8310

Pre-Production

PP, May 2012, Rev 3.1

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

If ICE is selected (OTP_MEM = 0):

00 = Page 2

01 = Page 3

10 = Page 4

11 = Reserved

Table 27 OTP Memory Control

14.5 OTP / ICE INTERRUPTS

The OTP and ICE memories are associated with two Interrupt event flags.

The OTP_CMD_END_EINT interrupt is set each time an OTP / ICE Command has completed or if

OTP Auto-Program has completed. (See Section 14.4 for a definition of the OTP and ICE

Commands. See Section 14.6.3 for details of the OTP Auto-Program function.)

The OTP_ERR_EINT interrupt is set when an OTP / ICE Error has occurred. The errors detected

include ICE Read Failure, OTP Verify Failure and attempted OTP Write to a page that has been

Finalised.

Each of these secondary interrupts triggers a primary OTP Memory Interrupt, OTP_INT (see

Section 23). This can be masked by setting the mask bit(s) as described in Table 70.

Note that OTP_CMD_END_EINT is triggered during the normal start-up and shutdown operations,

when the WM8310 accesses the OTP and/or ICE memories. For typical applications, it is

recommended that the OTP_CMD_END_EINT interrupt should be masked at all times except when

performing user-initiated OTP/DBE commands.

ADDRESS

BIT

LABEL

DESCRIPTION

R16402

(4012h)

Interrupt Status

OTP_CMD_END_EINT

OTP / ICE Command End interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

OTP_ERR_EINT

OTP / ICE Command Fail interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

R16410

(401Ah)

Interrupt Status

2 Mask

IM_OTP_CMD_END_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

IM_OTP_ERR_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

Table 28 OTP Memory Interrupts

14.6 DCRW MEMORY CONTENTS

The DCRW is the ICE/OTP Register Window, as described in Section 14.2. Under normal operating

conditions, this memory area is initialised with data from the integrated OTP or an external ICE

memory. The DCRW memory addresses range from R30720 (7800h) to R30759 (7827h). The

complete register map definition is described in Section 28.

The register fields in the DCRW allow the start-up configuration of the DC-DC Converters, the LDO

Regulators, GPIO pins 1-6 and Status LED outputs to be programmed. The DCRW also provides

control of the Battery Charger, Clocking, USB Current Limit and the Start-Up (SYSOK) voltage

threshold.

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