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WM8326 Datasheet(PDF) 134 Page - Wolfson Microelectronics plc |
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WM8326 Datasheet(HTML) 134 Page - Wolfson Microelectronics plc |
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134 / 255 page  WM8326 Production Data w PD, June 2012, Rev 4.0 134 VSYSOK VPVDD time VSYSLO VSHUTDOWN SYSOK (SYSLO) SHUTDOWN time time Figure 27 PVDD Monitoring ADDRESS BIT LABEL DEFAULT DESCRIPTION R16385 (4001h) PVDD Control 15:14 SYSLO_ERR_ ACT 00 SYSLO Error Action Selects the action taken when SYSLO is asserted 00 = Interrupt 01 = WAKE transition 10 = Reserved 11 = OFF transition 11 SYSLO_STS 0 SYSLO Status 0 = Normal 1 = PVDD is below SYSLO threshold 6:4 SYSLO_THR [2:0] 010 SYSLO threshold (falling PVDD) This is the falling PVDD voltage at which SYSLO will be asserted 000 = 2.8V 001 = 2.9V … 111 = 3.5V 2:0 SYSOK_THR [2:0] 101 SYSOK threshold (rising PVDD) This is the rising PVDD voltage at which SYSOK will be asserted 000 = 2.8V 001 = 2.9V … 111 = 3.5V Note that the SYSOK hysteresis margin is added to these threshold levels. Table 78 PVDD Monitoring Control |
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