AD9250 datasheet(35/44 Pages) AD

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Data Sheet

AD9250

Rev. 0 | Page 35 of 44

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Each row in the memory map register table has eight bit locations.

The memory map is roughly divided into three sections: the

chip configuration registers (Address 0x00 to Address 0x02);

the channel index and transfer registers (Address 0x05 and

Address 0xFF); and the ADC functions registers, including

setup, control, and test (Address 0x08 to Address 0xA8).

The memory map register table (see Table 17) documents the

default hexadecimal value for each hexadecimal address shown.

The column with the heading Bit 7 (MSB) is the start of the

default hexadecimal value given. For example, Address 0x14,

the output mode register, has a hexadecimal default value of

0x01. This means that Bit 0 = 1, and the remaining bits are 0s.

This setting is the default output format value, which is twos

complement. For more information on this function and others,

see the AN-877 Application Note, Interfacing to High Speed

ADCs via SPI. This document details the functions controlled

by Register 0x00 to Register 0x25. The remaining registers,

Memory Map Register Description section.

Open and Reserved Locations

All address and bit locations that are not included in Table 17

are not currently supported for this device. Unused bits of a

valid address location should be written with 0s. Writing to these

locations is required only when part of an address location is

open (for example, Address 0x18). If the entire address location

is open (for example, Address 0x13), do not write to this address

location.

Default Values

After the AD9250 is reset, critical registers are loaded with

default values. The default values for the registers are given in

the memory map register table, Table 17.

Logic Levels

An explanation of logic level terminology follows:

•

“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

•

“Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

Transfer Register Map

Address 0x09, Address 0x0B, Address 0x14, Address 0x18, and

Address 0x3A to Address 0x4C are shadowed. Writes to these

addresses do not affect part operation until a transfer command

is issued by writing 0x01 to Address 0xFF, setting the transfer

bit. This allows these registers to be updated internally and

simultaneously when the transfer bit is set. The internal update

takes place when the transfer bit is set, and then the bit autoclears.

Channel-Specific Registers

Some channel setup functions, such as the signal monitor

thresholds, can be programmed to a different value for each

channel. In these cases, channel address locations are internally

duplicated for each channel. These registers and bits are designated

in Table 17 as local. These local registers and bits can be accessed

by setting the appropriate Channel A or Channel B bits in

the registers of both channels. In a read cycle, only Channel A

or Channel B should be set to read one of the two registers. If

both bits are set during an SPI read cycle, the part returns the

value for Channel A. Registers and bits designated as global in

Table 17 affect the entire part and the channel features for which

independent settings are not allowed between channels. The

settings in Register 0x05 do not affect the global registers and bits.

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