AD9250 datasheet(28/44 Pages) AD

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AD9250

Data Sheet

Rev. 0 | Page 28 of 44

Digital Outputs and Timing

The AD9250 has differential digital outputs that power up by

default. The driver current is derived on-chip and sets the output

current at each output equal to a nominal 4 mA. Each output

presents a 100 Ω dynamic internal termination to reduce

unwanted reflections.

Place a 100 Ω differential termination resistor at each receiver

input to result in a nominal 300 mV peak-to-peak swing at

the receiver (see Figure 53). Alternatively, single-ended 50 Ω

termination can be used. When single-ended termination is

used, the termination voltage should be DRVDD/2; otherwise,

ac coupling capacitors can be used to terminate to any single-

ended voltage.

100Ω

DIFFERENTIAL

TRACE PAIR

SERDOUTx+

DRVDD

VRXCM

SERDOUTx–

VCM = Rx VCM

OUTPUT SWING = 300mV p-p

0.1µF

RECEIVER

Figure 53. AC-Coupled Digital Output Termination Example

The AD9250 digital outputs can interface with custom ASICs and

FPGA receivers, providing superior switching performance in

noisy environments. Single point-to-point network topologies are

recommended with a single differential 100 Ω termination resistor

placed as close to the receiver logic as possible. The common

mode of the digital output automatically biases itself to half the

supply of the receiver (that is, the common-mode voltage is 0.9 V

for a receiver supply of 1.8 V) if dc-coupled connecting is used

(see Figure 54). For receiver logic that is not within the bounds

of the DRVDD supply, use an ac-coupled connection. Simply

place a 0.1 µF capacitor on each output pin and derive a 100 Ω

differential termination close to the receiver side.

100Ω

DIFFERENTIAL

TRACE PAIR

DRVDD

VCM = DRVDD/2

OUTPUT SWING = 300mV p-p

RECEIVER

SERDOUTx+

SERDOUTx–

Figure 54. DC-Coupled Digital Output Termination Example

If there is no far-end receiver termination, or if there is poor

differential trace routing, timing errors may result. To avoid

such timing errors, it is recommended that the trace length be

less than six inches, and that the differential output traces be

close together and at equal lengths.

Figure 55 shows an example of the digital output (default) data eye

and time interval error (TIE) jitter histogram and bathtub curve for

the AD9250 lane running at 5 Gbps.

Additional SPI options allow the user to further increase the

output driver voltage swing of all four outputs to drive longer

trace lengths (see Register 0x15 in Table 17). The power

dissipation of the DRVDD supply increases when this option is

used. See the Memory Map section for more details.

The format of the output data is twos complement by default.

To change the output data format to offset binary, see the

Memory Map section (Register 0x14 in Table 17).

–0.5

0.5

ULS

PERIOD1: HISTOGRAM

6000

7000

–10

TIME (ps)

5000

4000

1000

2000

3000

1–16

1–14

1–12

1–10

1–8

1–6

1–4

1–2

–

–100

–200

100

200

TIME (ps)

400

300

200

100

–100

–300

–400

–200

HEIGHT1: EYE DIAGRAM

–

TJ@BER1: BATHTUB

EYE: TRANSITION BITS OFFSET: –0.0072

ULS: 8000; 999992 TOTAL: 8000.999992

0.78 UI

Figure 55. AD9250 Digital Outputs Data Eye, Histogram and Bathtub, External 100 Ω Terminations at 5 Gbps

AD9250 Datasheet(PDF) 28 Page - Analog Devices

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