AD9250 datasheet(41/44 Pages) AD

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Data Sheet

AD9250

Rev. 0 | Page 41 of 44

APPLICATIONS INFORMATION

DESIGN GUIDELINES

Before starting system level design and layout of the AD9250, it

is recommended that the designer become familiar with these

guidelines, which discuss the special circuit connections and

layout requirements needed for certain pins.

Power and Ground Recommendations

When connecting power to the AD9250, it is recommended that

two separate 1.8 V power supplies be used: the power supply for

AVDD can be isolated and for DVDD and DRVDD it can be

tied together, in which case an isolation inductor of approximately

1 µH is recommended. Alternately, the JESD204B PHY power

(DRVDD) and analog (AVDD) supplies can be tied together,

and a separate supply can be used for the digital outputs (DVDD).

The designer can employ several different decoupling capacitors

to cover both high and low frequencies. Locate these capacitors

close to the point of entry at the PC board level and close to the

pins of the part with minimal trace length.

When using the AD9250, a single PCB ground plane should be

sufficient. With proper decoupling and smart partitioning of the

PCB analog, digital, and clock sections, optimum performance

is easily achieved.

Exposed Paddle Thermal Heat Slug Recommendations

It is mandatory that the exposed paddle on the underside of the

ADC be connected to analog ground (AGND) to achieve the

best electrical and thermal performance. Mate a continuous,

exposed (no solder mask) copper plane on the PCB to the

AD9250 exposed paddle, Pin 0.

The copper plane should have several vias to achieve the lowest

possible resistive thermal path for heat dissipation to flow through

the bottom of the PCB. These vias should be filled or plugged with

nonconductive epoxy.

To maximize the coverage and adhesion between the ADC and

the PCB, overlay a silkscreen to partition the continuous plane

on the PCB into several uniform sections. This provides several tie

points between the ADC and the PCB during the reflow process.

Using one continuous plane with no partitions guarantees only

one tie point between the ADC and the PCB. See the evaluation

board for a PCB layout example. For detailed information about

the packaging and PCB layout of chip scale packages, refer to

the AN-772 Application Note, A Design and Manufacturing

Guide for the Lead Frame Chip Scale Package (LFCSP).

VCM

Decouple the VCM pin to ground with a 0.1 µF capacitor, as

shown in Figure 36. For optimal channel-to-channel isolation,

include a 33 Ω resistor between the AD9250 VCM pin and the

Channel A analog input network connection, as well as between

the AD9250 VCM pin and the Channel B analog input network

connection.

SPI Port

When the full dynamic performance of the converter is required,

do not activate the SPI port during periods. Because the

SCLK, CS, and SDIO signals are typically asynchronous to the

ADC clock, noise from these signals can degrade converter

performance. If the on-board SPI bus is used for other devices, it

may be necessary to provide buffers between this bus and the

AD9250 to keep these signals from transitioning at the converter

input pins during critical sampling periods.

AD9250 Datasheet(PDF) 41 Page - Analog Devices

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