AD9250 datasheet(36/44 Pages) AD

36 / 44 page

AD9250

Data Sheet

Rev. 0 | Page 36 of 44

MEMORY MAP REGISTER TABLE

All address and bit locations that are not included in Table 17 are not currently supported for this device.

Table 17. Memory Map Registers

Reg

Addr

(Hex)

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Default

Notes

0x00

Global SPI

config

LSB first

Soft reset

LSB first

0x18

0x01

CHIP ID

AD9250 8-bit CHIP ID is 0xB9

0xB9

Read

only

0x02

Chip info

Speed grade

00 = 250 MSPS

11 = 170 MSPS

Reserved for chip die revision currently

0x0

0x00

or 0x30

0x05

Channel

index

SPI write

to ADC B

path

SPI write to

ADC A path

0x03

0x08

PDWN

modes

External

PDWN

mode;

0 = PDWN

is full

power

down;

1 = PDWN

puts

device in

standby

JTX in

standby;

0 = 204B

core is

unaffected

standby;

1: 204B

core is

powered

down

except for

PLL during

standby

JESD204B power modes;

00 = normal mode

(power up);

01 = power-down mode:

PLL off, serializer off,

clocks stopped, digital

held in reset;

10 = standby mode: PLL

on, serializer off, clocks

stopped, digital held in

reset

Chip power modes;

00 = normal mode

(power up);

01 = power-down mode,

digital datapath clocks

disabled, digital

datapath held in reset;

most analog paths

powered off;

10 = standby mode;

digital datapath clocks

disabled, digital

datapath held in reset,

some analog paths

powered off

0x00

0x09

Global clock

Reserved

Clock selection:

00 = Nyquist clock

10 = RF clock divide by 4

11 = clock off

Clock duty

cycle

stabilizer

enable

0x01

DCS

enabled

if clock

divider

enabled

0x0A

PLL status

PLL locked

status

204B link is

ready

Read

only

0x0B

Global clock

divider

Clock divide phase relative to the

encode clock;

0x0 = 0 input clock cycles delayed;

0x1 = 1 input clock cycles delayed;

0x2 = 2 input clock cycles delayed;

…..

0x7 = 7 input clock cycles delayed

Clock divider ratio relative to the

encode clock;

0x00 = divide by 1;

0x01 = divide by 2;

0x02 = divide by 3;

…..

0x7 = divide by 8;

using a CLKDIV_DIVIDE_RATIO > 0

(Divide Ratio > 1) causes the DCS to be

automatically enabled

0x00

0x0D

Test control

reg

User test mode cycle;

00 = repeat pattern

(user pattern 1, 2, 3, 4, 1,

2, 3, 4, 1, …);

10 = single pattern (user

pattern 1, 2, 3, 4, then all

zeros)

Long

psuedo

random

number

generator

reset;

0 = long

PRN

enabled;

1 = long

PRN held

in reset

Short

psuedo

random

number

generator

reset;

0 = short

PRN

enabled;

1 = short

PRN held

in reset

Data output test generation mode;

0000 = off (normal mode);

0001 = midscale short;

0010 = positive Full scale;

0011 = negative full scale;

0100 = alternating checker board;

0101 = PN sequence long;

0110 = PN sequence short;

0111 = 1/0 word toggle;

1000 = user test mode (use with Register 0x0D, Bit[7]

and user pattern 1, 2, 3, 4);

1001 to 1110 = unused;

1111 = ramp output

0x00

0x0E

BIST test

Reset BIST

BIST enable

0x00

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