REV. 0

AD7866

–14–

100nF

2.5V

REF

ADC B

EXT REF

EXT REF

470nF

EXT REF

470nF

BUF B

ADC A

BUF A

Figure 15. Reference Circuit

being applied elsewhere as it will not be capable of sourcing more

than a few microamps. If the reference voltage is taken from

sary. Either pin is capable of sourcing current in the region of

100

µA; however, the larger the source current requirement, the

greater the voltage drop seen at the pin. The output impedance of

each of these pins is typically 50

Ω. In addition, this point repre-

sents the actual voltage applied to the ADC internally so any

voltage drop due to the current load or disturbance due to a

dynamic load will directly affect the ADC conversion. For

this reason, if a large current source is necessary, or a dynamic

load is present, it is recommended to use a buffer on the output

to drive a device.

Examples of suitable external reference devices that may be

REF43, or AD1582.

MODES OF OPERATION

The mode of operation of the AD7866 is selected by controlling

the (logic) state of the

CS signal during a conversion. There

are three possible modes of operation, Normal Mode, Partial

Power-Down Mode, and Full Power-Down Mode. The point at

which

CS is pulled high after the conversion has been initiated

will determine which power-down mode, if any, the device will

enter. Similarly, if already in a power-down mode,

CS can

control whether the device will return to normal operation or

remain in power-down. These modes of operation are designed

to provide flexible power management options. These options

can be chosen to optimize the power dissipation/throughput

rate ratio for differing application requirements.

Normal Mode

This mode is intended for fastest throughput rate performance as

the user does not have to worry about any power-up times with

the AD7866 remaining fully powered all the time. Figure 16 shows

the general diagram of the operation of the AD7866 in this mode.

The conversion is initiated on the falling edge of

CS as described in

the Serial Interface section. To ensure the part remains fully pow-

ered up at all times

CS must remain low until at least 10 SCLK

falling edges have elapsed after the falling edge of

CS. If CS is

brought high any time after the 10th SCLK falling edge, but before

the 16th SCLK falling edge, the part will remain powered up but

back into three-state. Sixteen serial clock cycles are required to

complete the conversion and access the conversion result. The

elapsed, but instead when

CS is brought high again. If CS is left

low for a further 16 SCLK cycles then the result from the other

shown in Figure 22 (see Serial Interface section). The STATUS

bits provided prior to each conversion result will identify which

ADC the following result will be from. Once 32 SCLK cycles

SCLK falling edge. If

CS is brought high prior to this, the D

will return to three-state at that point. Hence,

CS may idle low after

32 SCLK cycles, until it is brought high again sometime prior to the

next conversion (effectively idling

CS low), if so desired, as the bus

will still return to three-state upon completion of the dual result read.

returned to three-state, another conversion can be initiated after

Partial Power-Down Mode

This mode is intended for use in applications where slower

throughput rates are required. Either the ADC is powered down

between each conversion, or a series of conversions may be per-

formed at a high throughput rate and the ADC is then powered

down for a relatively long duration between these bursts of several

conversions. When the AD7866 is in Partial Power-Down, all

analog circuitry is powered down except for the on-chip reference

and reference buffer.

SCLK

CS

STATUS BITS AND CONVERSION RESULT

1

16

10

Figure 16. Normal Mode Operation