AD7866 datasheet(20/20 Pages) AD

20 / 20 page

REV. 0

–20–

AD7866

shielding. Both AGND pins of the AD7866 should be sunk in the

AGND plane. Digital and analog ground planes should be joined

at only one place. If the AD7866 is in a system where multiple

devices require an AGND-to-DGND connection, the connection

should still be made at one point only, a star ground point that

should be established as close as possible to the AD7866.

Avoid running digital lines under the device as these will couple

noise onto the die. The analog ground plane should be allowed

to run under the AD7866 to avoid noise coupling. The power

supply lines to the AD7866 should use as large a trace as pos-

sible to provide low impedance paths and reduce the effects of

glitches on the power supply line. Fast switching signals like

clocks should be shielded with digital ground to avoid radiating

noise to other sections of the board, and clock signals should

never be run near the analog inputs. Avoid crossover of digital

and analog signals. Traces on opposite sides of the board should

run at right angles to each other. This will reduce the effects of

feedthrough through the board. A microstrip technique is by far

the best but is not always possible with a double-sided board. In

this technique, the component side of the board is dedicated to

ground planes while signals are placed on the solder side.

Good decoupling is also important. All analog supplies should be

decoupled with 10

µF tantalum in parallel with 0.1 µF capacitors

to AGND. All digital supplies should have at least a 0.1

µF disc

ceramic capacitor to DGND. VDRIVE should have a 0.1

µF ceramic

capacitor to DGND. To achieve the best from these decoupling

components, they must be placed as close as possible to the device,

ideally right up against the device. The 0.1

µF capacitors should

have low Effective Series Resistance (ESR) and Effective Series

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

20-Lead Thin Shrink Small Outline Package

(RU-20)

0.256 (6.50)

0.246 (6.25)

0.177 (4.50)

0.169 (4.30)

PIN 1

0.260 (6.60)

0.252 (6.40)

SEATING

PLANE

0.006 (0.15)

0.002 (0.05)

0.0118 (0.30)

0.0075 (0.19)

0.0256 (0.65)

BSC

0.0433 (1.10)

MAX

0.0079 (0.20)

0.0035 (0.090)

0.028 (0.70)

0.020 (0.50)

Inductance (ESI), such as common ceramic or surface mount types,

which provide a low impedance path to ground at high frequen-

cies to handle transient currents due to internal logic switching.

Figure 27 shows the recommended supply decoupling scheme.

For information on the decoupling requirements of each reference

configuration, see the Reference section.

AGND

DGND

AD7866

DVDD

AVDD

0.1 F10 F

AGND

0.1 F

10 F

VDRIVE

0.1 F

Figure 27. Recommended Supply Decoupling Scheme

Evaluating the AD7866 Performance

The recommended layout for the AD7866 is outlined in the evalu-

ation board for the AD7866. The evaluation board package includes

a fully assembled and tested evaluation board, documentation, and

software for controlling the board from the PC via the EVAL-

BOARD CONTROLLER. The EVAL-BOARD CONTROLLER

can be used in conjunction with the AD7866 Evaluation board, as

well as many other Analog Devices evaluation boards ending in the

CB designator, to demonstrate/evaluate the ac and dc performance

of the AD7866.

The software allows the user to perform ac (fast Fourier transform)

and dc (histogram of codes) tests on the AD7866.

AD7866 Datasheet(PDF) 20 Page - Analog Devices

AD7866 Datasheet(HTML) 20 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL