REV. 0

AD9218

–17–

PCB Bill of Materials

#

Qty

REFDES

Device

Package

Value

1

29

C1, C3–C15, C20–C25, C27–C35

Capacitor

0603

0.1

µF

2

2

C2, C36

Capacitor

0603

15 pF

3

7

C16, C17, C18, C19, C26, C37, C38

Capacitor

TAJD

10

µF

6

8

J1, J2, J3, J4, J5, J6, J7, J8

Connector

SMB

7

3

P1, P4, P11

4-Pin Power Connector

TB4

Wieland

25.531.3425.0

Z5.602.5453.0

8

2

P2, P3

HEADER40

10

8

R1–R4, R22–R24, R30

Resistor

0603

25

Ω

11

10

R5–R12, R34, R37

Resistor

0603

50

Ω

12

2

R13, R14

Resistor

0603

2 k

Ω

13

6

R15, R17, R18, R26, R29, R31

Resistor

0603

500

Ω

14

2

R16, R25

Resistor

0603

525

Ω

15

2

R19, R27

Resistor

0603

4 k

Ω

16

8

R20, R32, R33, R35, R36, R38–R40

Resistor

0603

0

Ω

17

2

R21, R28

Resistor

0603

1 k

Ω

18

2

T1, T2

Transformer

ADT-1-1WT

Minicircuits

19

1

U1

AD9218

LQFP48

20

2

U2, U3

74LCX821

SO24M3

21

1

U4

AD9763

LQFP48

22

2

U5, U6

74LCX86

SO14

23

4

U7, U8, U9, U10

Resistor Array

CTS20

22

Ω

24

2

U11, U12

AD8138

SO8NB

NOTE

R22, R23, R24, R30, R32, R33, R35, R36, R38, R39, R40, C2, C36 not placed on board.

Data Outputs

The ADC digital outputs are latched on the board by two

LCX821s, the latch outputs are available at the two 40-pin

connectors at Pins 23–33 on P3 (Channel A) and Pins 23–33 on

P4 (Channel B). The latch output clocks (data ready) are avail-

able at Pin 4 on P3 (Channel A) and Pin 4 on P4 (Channel B).

The data ready signal on Channel B can be aligned with Clock

A input by connecting E43–E42 or aligned with Clock B input

by connecting E42–E33.

M 10.0ns

CH4

40mV

PIN 31 (DATA)

PIN 37 (CLOCK)

T

Figure 15. Data Output and Clock at 80-Pin Connector

DAC Outputs

Each channel is reconstructed by an on-board dual channel DAC,

an AD9763. This DAC is intended to assist in debug only. It

should not be used to measure the performance of the ADC.

It is a current output DAC with on-board 50

Ω termination

resistors. Figure 16 is representative of the DAC output with a

full-scale analog input. The scope setting was low bandwidth,

50

Ω termination.

CH1

500mV

M 50.0ns

CH1

380mV

1

T

Figure 16. DAC Output