AD9834

–5–

REV PrM

PRELIMINARY TECHNICAL DATA

PIN FUNCTIONS DESCRIPTIONS

Pin # Mnemonic

Function

ANALOG SIGNAL AND REFERENCE

1

FS ADJUST

Full-Scale Adjust Control.

This

determines the magnitude of the full-scale DAC current.

the full-scale current is as follows:

Ω typical

2

REFOUT

Voltage Reference Output.

The AD9834 has an internal 1.20 V reference, which is made

available at this pin.

3

COMP

A DAC Bias Pin. This pin is used for de-coupling the DAC bias voltage.

17

VIN

Input to comparator. The comparator can be used to generate a square wave from the

sinusoidal DAC output. The DAC output should be filtered appropriately before being applied

to the comparator to improve jitter.

When bits OPBITEN and SIGNPIB in the control

register are set to 1, the comparator input is connected to VIN.

19,20 IOUT, IOUTB

Current Output. This is a high impedance current source. A load resistor of nominally 200

Ω

should be connected between IOUT and AGND. IOUTB should preferably be tied through an

external load resistor of 200

Ω to AGND but can be tied directly to AGND. A 20pF capacitor

to AGND is also recommended to prevent clock feedthrough.

POWER SUPPLY

4

AVDD

Positive power supply for the analog section. AVDD can have a value from +2.3 V to +5.5 V.

A 0.1 µF decoupling capacitor should be connected between AVDD and AGND.

5

DVDD

Positive power supply for the digital section. DVDD can have a value from +2.3 V to +5.5 V.

A 0.1 µF decoupling capacitor should be connected between DVDD and DGND.

6

CAP/2.5V

The digital circuitry operates from a +2.5 V power supply.

This +2.5 V is generated from

DVDD using an on board regulator (when DVDD exceeds +2.7 V).

The regulator requires a

decoupling capacitor of typically 100 nF which is connected from CAP/2.5V to DGND.

If

DVDD is equal to or less than +2.7 V, CAP/2.5 V should be shorted to DVDD.

7

DGND

Digital Ground.

18

AGND

Analog Ground.

DIGITAL INTERFACE AND CONTROL

8

MCLK

Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the

frequency of MCLK. The output frequency accuracy and phase noise are determined by this

clock.

9

FSELECT

Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is

used in the phase accumulator. The frequency register to be used can be selected using the pin

FSELECT or the bit FSEL. When the bit FSEL is being used to select the frequency register,

this pin, FSELECT, should be tied to CMOS high or low.

10

PSELECT

Phase Select Input. PSELECT controls which phase register, PHASE0 or PHASE1, is added

to the phase accumulator output. The phase register to be used can be selected using the pin

PSELECT or the bit PSEL. When the phase registers are being controlled by the bit PSEL,

this pin, PSELECT, should be tied to CMOS high or low.

11

RESET

Active high digital input. RESET resets appropriate internal registers to zero which

corresponds to an analog output of midscale. RESET does not affect any of the addressable

registers.

12

SLEEP

Active high digital input. When this pin is high, the DAC is powered down. This pin has the

same function as control bit SLEEP12.

13

SDATA

Serial Data Input. The 16-bit serial data word is applied to this input.

14

SCLK

Serial Clock Input. Data is clocked into the AD9834 on each falling SCLK edge.

15

FSYNC

Active Low Control Input. This is the frame synchronisation signal for the input data. When

FSYNC is taken low, the internal logic is informed that a new word is being loaded into

the device.

16

SIGN BIT OUT Logic Output. The comparator output is available on this pin or, alternatively, the MSB from

the NCO can be output on this pin. Setting bit OPBITEN in the control register to 1 enables

this output pin. Bit SIGNPIB determines whether the comparator output or the MSB from

the NCO is output on the pin.