AD9834 datasheet(18/20 Pages) AD

18 / 20 page

AD9834

–18–

REV PrM

PRELIMINARY TECHNICAL DATA

ferred should FSYNC be taken high again.

Figure 12. 68HC11/68L11 to AD9834 Interface

AD9834 to 80C51/80L51 Interface

Figure 14 shows the serial interface between the AD9834

and the 80C51/80L51 microcontroller. The

microcontroller is operated in mode 0 so that TXD of the

80C51/80L51 drives SCLK of the AD9834 while RXD

drives the serial data line SDATA. The FSYNC signal is

again derived from a bit programmable pin on the port

(P3.3 being used in the diagram). When data is to be

transmitted to the AD9834, P3.3 is taken low. The

80C51/80L51 transmits data in 8 bit bytes thus, only 8

falling SCLK edges occur in each cycle. To load the re-

maining 8 bits to the AD9834, P3.3 is held low after the

first 8 bits have been transmitted and a second write op-

eration is initiated to transmit the second byte of data.

P3.3 is taken high following the completion of the second

write operation. SCLK should idle high between the two

write operations. The 80C51/80L51 outputs the serial

data in a format which has the LSB first.

The AD9834

accepts the MSB first (the 4 MSBs being the control in-

formation, the next 4 bits being the address while the 8

LSBs contain the data when writing to a destination regis-

ter). Therefore, the transmit routine of the 80C51/80L51

must take this into account and re-arrange the bits so that

the MSB is output first.

Figure 13. 80C51/80L51 to AD9834 Interface

AD9834 to DSP56002 Interface

Figure 15 shows the interface between the AD9834 and

the DSP56002. The DSP56002 is configured for normal

mode asynchronous operation with a Gated internal clock

(SYN = 0, GCK = 1, SCKD = 1). The frame sync pin is

generated internally (SC2 = 1), the transfers are 16 bits

wide (WL1 = 1, WL0 = 0) and the frame sync signal will

frame the 16 bits (FSL = 0). The frame sync signal is

available on pin SC2 but, it needs to be inverted before

being applied to the AD9834. The interface to the

DSP56000/DSP56001 is similar to that of the DSP56002.

Figure 14. AD9834 to DSP56002 Interface

AD9834 EVALUATION BOARD

The AD9834 Evaluation Board allows designers to evalu-

ate the high performance AD9834 DDS modulator with

minimum of effort.

To prove that this device will meet the user's waveform

synthesis requirements, the user only require's a power-

supply, an IBM-compatible PC and a spectrum analyser

along with the evaluation board.

The DDS evaluation kit includes a populated, tested

AD9834 printed circuit board. The evaluation board in-

terfaces to the parallel port of an IBM compatible PC.

Software is available with the evaluation board which al-

lows the user to easily program the AD9834. A schematic

of the Evaluation board is shown in Figure 24. The soft-

ware will run on any IBM compatible PC which has

Microsoft Windows95, Windows98 or Windows ME 2000

NT™ installed.

Using the AD9834 Evaluation Board

The AD9834 Evaluation kit is a test system designed to

simplify the evaluation of the AD9834. An application

note is also available with the evaluation board and gives

full information on operating the evaluation board.

Prototyping Area

An area is available on the evaluation board for the user to

add additional circuits to the evaluation test set. Users

may want to build custom analog filters for the output or

add buffers and operational amplifiers to be used in the

final application.

XO vs. External Clock

The AD9834 can operate with master clocks up to

50MHz. A 50MHz oscillator is included on the evaluation

board. However, this oscillator can be removed and, if

required, an external CMOS clock connected to the part.

Power Supply

Power to the AD9834 Evaluation Board must be provided

externally through pin connections. The power leads

should be twisted to reduce ground loops.

AD9834 Datasheet(PDF) 18 Page - Analog Devices

AD9834 Datasheet(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL