AD9834

–11–

REV PrM

PRELIMINARY TECHNICAL DATA

Table 2. Description of bits in the Control Register

Bit

Name

Function

D13

B28

Two write operations are required to load a complete word into either of the Frequency registers.

B28 = '1' allows a complete word to be loaded into a frequency register in two consecutive

writes. The first write contains the 14 LSBs of the frequency word and the next write will

contain the 14 MSBs. The first two bits of each sixteen-bit word define the frequency register to

which the word is loaded, and should therefore be the same for both of the consecutive writes.

Refer to table 6 for the appropriate addresses. The write to the frequency register occurs after both

words have been loaded, so the register never holds an intermediate value. An example of a com-

plete 28-bit write is shown in table 7.

When B28 = '0' the 28-bit frequency register operates as 2 14-bit registers, one containing the 14

MSBs and the other containing the 14 LSBs.

This means that the 14 MSBs of the frequency

word can be altered independent of the 14 LSBs and vice versa. To alter the 14 MSBs or the 14

LSBs, a single write is made to the appropriate Frequency address. The control bit D12 (HLB)

informs the AD9834 whether the bits to be altered are the 14 MSBs or 14 LSBs.

D12

H L B

This control bit allows the user to continuously load the MSBs or LSBs of a frequency regiser

while ignoring the remaining 14 bits. This is useful if the complete 28 bit resolution is not re-

quired. HLB is used in conjunction with D13 (B28). This control bit indicates whether the 14 bits

being loaded are being transferred to the 14 MSBs or 14 LSBs of the addressed frequency regis-

ter. D13 (B28) must be set to '0' to be able to change the MSBs and LSBs of a frequency word

seperately. When D13 (B28) = '1', this control bit is ignored.

HLB = '1' allows a write to the 14 MSBs of the addressed frequency register.

HLB = '0' allows a write to the 14 LSBs of the addressed frequency register.

D11

FSEL

The FSEL bit defines whether the FREQ0 register or the FREQ1 register is used in the phase

accumulator. See table 4 on selecting a frequency register.

D10

PSEL

The PSEL bit defines whether the PHASE0 register or the PHASE1 register data is added to the

output of the phase accumulator. See Table 5 on selecting a phase register.

D 9

PIN/SW

Functions that select frequency and phase registers, reset internal registers, and power down the

DAC can be implemented using either software or hardware. PIN/SW selects the source of

control for these functions.

PIN/SW = '1' implies that the functions are being controlled using the appropriate control pins.

PIN/SW = '0' implies that the functions are being controlled using the appropriate control bits.

D 8

RESET

RESET = '1' resets internal registers to zero, which corresponds to an analog output of midscale.

RESET = '0' disables Reset. This function is explained further in Table 11.

D 7

SLEEP1

When SLEEP1 = '1', the internal MCLK clock is disabled. The DAC output will remain at its

present value as the NCO is no longer accumulating.

When SLEEP1 = '0' MCLK is enabled. This function is explained further in Table 12.

D 6

SLEEP12

SLEEP12 = '1'

powers down the on-chip DAC. This is useful when the AD9834 is used to output

the MSB of the DAC data.

SLEEP12 = '0' implies that the DAC is active. This function is explained further in Table 12.

D 5

OPBITEN

The function of this bit is to control whether there is an output at the pin SIGN BIT OUT. This

bit should remain at '0' if the user is not using the pin SIGN BIT OUT.

OPBITEN = '1' enables the pin SIGN BIT OUT.

When OPBITEN equals 0, the SIGN BIT OUT output buffer is put into a high impedance state

and, therefore, no output is available at the SIGN BIT OUT pin.

D 4

SIGNPIB

The function of this bit is to control what is output at the pin SIGN BIT OUT.

When SIGNPIB = '1', the on board comparator is connected to SIGN BIT OUT.

After filtering

the sinusoidal output from the DAC, the waveform can be applied to the comparator to generate a

square waveform. This is explained futher in Table 13.

When SIGNPIB = '0', the MSB (or MSB/2) of the DAC data is connected to the pin SIGN BIT

OUT. The bit DIV2 controls whether it is the MSB or MSB/2 that is ouput.

D 3

DIV2

DIV2 is used in association with SIGNPIB and OPBITEN. This is fully explained in Table 13.

When DIV2 = '1', the digital output

is passed directly to the SIGN BIT OUT pin.

When DIV2 = '0', the digital output/2

is passed directly to the SIGN BIT OUT pin.

D 2

Reserved

This bit must always be set to 0.

D 1

MODE

The function of this bit is to control what is output at the IOUT/IOUT pins. This bit should be

set to '0' if the control bit OPBITEN = '1'.

When MODE = '1', the SIN ROM is bypassed, resulting in a ramp output from the DAC.

When MODE = '0' the SIN ROM is used to convert the phase information into amplitude infor-

mation which results in a sinusoidal signal at the output (See table 14).

D 0

Reserved

This bit must always be set to 0.