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AD9834

–3–

REV PrM

PRELIMINARY TECHNICAL DATA

TIMINGCHARACTERISTICS1 (V

DD = +2.3 V to +5.5 V; AGND = DGND = 0 V, unless otherwise noted)

Parameter

Limit at TMIN to TMAX

Units

Test Conditions/Comments

ns min

MCLK Period

ns min

MCLK High Duration

ns min

MCLK Low Duration

ns min

SCLK Period

ns min

SCLK High Duration

ns min

SCLK Low Duration

ns min

FSYNC to SCLK Falling Edge Setup Time

ns min

FSYNC to SCLK Hold Time

t4 - 5

ns max

ns min

Data Setup Time

t10

ns min

Data Hold Time

t11

ns min

FSELECT, PSELECT Setup Time Before MCLK Rising Edge

t11A

ns min

FSELECT, PSELECT Setup Time After MCLK Rising Edge

1 Guaranteed by design, not production tested.

*See Pin Description Section.

Figure 3. Control Timing

Figure 2. Master Clock

Figure 4. Serial Timing

Figure 1. Test Circuit With which Specifications are tested.

IOUT

COMP

ADJUST

REFOUT

AD9834

ON-BOARD

REFERENCE

10-BIT DAC

SIN

ROM

FULL-SCALE

CONTROL

200R

20pF

RSET

6.8 K

10nF

AVDD

REGULATOR

100nF

CAP/2.5V

MCLK

t11A

t11

VALIDDATA

VALID DATA

VALIDDATA

MCLK

FSELECT,

PSELECT

SCLK

FSYNC

SDATA

t10

D15

D14

D15

D14

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