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AD9834

–12–

REV PrM

PRELIMINARY TECHNICAL DATA

The Frequency and Phase Resisters

The AD9834 contains 2 frequency registers and 2 phase

registers. These are described in Table 3 below.

Table 3. Frequency/Phase Registers

Size

Description

FREQ0

28 Bits Frequency Register 0. When FSEL

bit or FSELECT pin = 0, this regis-

ter defines the output frequency as a

fraction of the MCLK frequency.

FREQ1

28 Bits Frequency Register 1. When FSEL

bit or FSELECT pin = 1, this regis-

ter defines the output frequency as a

fraction of the MCLK frequency.

PHASE0

12 Bits Phase Offset Register 0. When PSEL

bit or PSELECT pin = 0, the con-

tents of this register are added to the

output of the phase accumulator.

PHASE1

12 Bits Phase Offset Register 1. When PSEL

bit or PSELECT pin = 1, the con-

tents of this register are added to the

output of the phase accumulator.

The analog output from the AD9834 is

fMCLK/2

28 x FREQREG

where FREQREG is the value loaded into the selected

frequency register. This signal will be phase shifted by

π/4096 x PHASEREG

where PHASEREG is the value contained in the selected

phase register.

Access to the frequency and phase registers is controlled

by both the FSELECT/PSELECT pins and the FSEL/

PSEL control bits. If the control bit PIN/SW = 1, the

pins controls the function, whereas if PIN/SW = 0, the

bits control the function. This is outlined in tables 4 and 5

below. If the FSEL/PSEL bits are being used, the pins

should preferably be held at CMOS logic high or low.

Control of the frequency/phase registers can be inter-

changed from the pins to the bits.

Table 4: Selecting a Frequency Register

FSELECT

FSEL

PIN/SW

Selected Register

FREQ0 REG

FREQ1 REG

FREQ0 REG

FREQ1 REG

Table 5: Selecting a Phase Register

PSELECT

PSEL

PIN/SW

Selected Register

PHASE0 REG

PHASE1 REG

PHASE0 REG

PHASE1 REG

The FSELECT and PSELECT pins are sampled on the

internal falling edge of MCLK. It is recommended that

the data on these pins does not change within a time win-

dow of the falling edge of MCLK (see Figure 3 for

timing). If FSELECT/PSELECT changes value when a

falling edge occurs, there is an uncertainty of one MCLK

cycle as to when control is transferred to the other fre-

quency/phase register.

The flow charts in Figures 8 and 9 show the routine for

selecting and writing to the frequency and phase registers

of the AD9834.

Writing to a Frequency Register:

When writing to a frequency register, bits D15 and D14

give the address of the frequency register.

Table 6. Frequency Register Bits

D15

D14

D13

D 0

MSB

14 FREQ0 REG BITS

LSB

MSB

14 FREQ1 REG BITS

LSB

If the user wishes to alter the entire contents of a fre-

quency register, two consecutive writes to the same

address must be performed, as the frequency registers are

28 bits wide. The first write will contain the 14 LSBs

while the second write will contain the 14 MSBs. For this

mode of operation, the control bit B28 (D13) should be

set to 1. An example of a 28-bit write is shown in Table 7

below.

Table 7: Writing 3FFF0000 to FREQ0 REG

SDATA input

Result of input word

0010 0000 0000 0000

Control word write (D15, D14 = 00);

B28 (D13) = 1; HLB (D12) = X

0100 0000 0000 0000

FREQ0 REG write (D15, D14 = 01);

14 LSBs = 0000

0111 1111 1111 1111

FREQ0 REG write (D15, D14 = 01);

14 MSBs = 3FFF

In some applications, the user does not need to alter all 28

bits of the frequency register.

With coarse tuning, only

the 14 MSBs are altered while with fine tuning, only the

14 LSBs are altered. By setting the control bit B28 (D13)

to 0, the 28-bit frequency register operates as 2 14-bit

registers, one containing the 14 MSBs and the other con-

taining the 14 LSBs. This means that the 14 MSBs of the

frequency word can be altered independent of the 14 LSBs

and vice versa. Bit HLB (D12) in the control register

identifies which 14 bits are being altered. Examples of this

are shown over.

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