EVAL-ADM1026EB datasheet(31/56 Pages) AD

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ADM1026

Rev. A | Page 31 of 56

Note that the THERM pin is bidirectional, so THERM may be

pulled low externally as an input. This causes the PWM and

DAC outputs to go to full scale until THERM is returned high

again. To disable THERM as an input, set Bit 0 of Configuration

prevents a low on Pin 42 from driving the fans at full speed.

THERM LIMIT

THERM LIMIT – 5°C

THERM

INT

INT CLEARED BY STATUS REG 1 READ,

BIT 2 OF CONFIG. REG. 1 SET, OR ARA

TEMPERATURE

Figure 54. Assertion of INT Due to THERM Event

Reset Input and Outputs

The ADM1026 has two active low, power-on reset outputs,

RESETMAIN and RESETSTBY. These operate as follows.

RESETSTBY monitors 3.3 V STBY. At power-up, RESETSTBY is

asserted (pulled low) until 180 ms after 3.3 V STBY rises above

the reset threshold.

RESETMAIN monitors 3.3 V MAIN. This means that at power-

up, RESETMAIN is asserted (pulled low) until 180 ms after

3.3 V MAIN rises above the reset threshold.

If 3.3 V MAIN rises with or before DVCC, RESETMAIN

remains asserted until 180 ms after RESETSTBY is negated.

RESETMAIN can also function as a RESET input. Pulling this

pin low resets the registers, which are initialized to their default

values by a software reset. (See the Software Reset Function

section for register details).

Note that the 3.3 V STBY pin supplies power to the ADM1026.

In applications that do not require monitoring of a 3.3 V STBY

and 3.3 V MAIN supply, these two pins should be connected

together (3.3 V MAIN should not be left floating).

To ensure that the 3.3 V STBY pin does not become backdriven,

the 3.3 V STBY supply should power on before all other voltages

in the system.

See Table 3 for more information about pin configuration.

RESETSTBY

RESETMAIN

3.3VMAIN

~1V

180ms

POWER-ON RESET

180ms

3.3VSTBY

~1V

Figure 55. Operation of Offset Outputs

NAND TREE TESTS

A NAND tree is provided in the ADM1026 for automated test

equipment (ATE) board-level connectivity testing. This allows

the functionality of all digital inputs to be tested in a simple

manner and any pins that are nonfunctional or shorted together

to be identified. The structure of the NAND tree is shown in

Figure 56. The device is placed into NAND tree test mode by

powering up with Pin 25 held high. This pin is sampled

automatically after power-up, and if it is connected high, then

the NAND test mode is invoked.

NTESTOUT

GPIO8

FAN0

FAN1

FAN2

FAN3

FAN4

FAN5

FAN6

SDA

SCL

FAN7

INT

GPIO9

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

Figure 56. NAND Tree

The NAND tree test may be carried out in one of two ways.

Start with all inputs low and take them high in turn,

starting with the input nearest to NTEST_OUT

(GPIO16/THERM) and working back up the tree to the

input furthest from NTESTOUT (INT). This should give

the characteristic output pattern shown in Figure 57, with

NTESTOUT toggling each time an input is taken high.

Start with all inputs high and take them low in turn,

starting with the input furthest from NTEST_OUT (INT)

and working down the tree to the input nearest to

NTEST_OUT (GPIO16/ THERM). This should give a

similar output pattern to Figure 58.

EVAL-ADM1026EB Datasheet(PDF) 31 Page - Analog Devices

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