EVAL-ADM1026EB datasheet(33/56 Pages) AD

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ADM1026

Rev. A | Page 33 of 56

Figure 60 shows the effect of one input being stuck high. Taking

GPIO12 high should take the output high. However, the next

input up the tree, GPIO11, is already high, so the output

immediately goes low again, causing a missing pulse in the

output pattern.

GPIO16

GPIO15

GPIO14

GPIO13

GPIO12

GPIO11

GPIO10

GPIO9

GPIO8

FAN0

FAN1

NTESTOUT

Figure 60. NAND Tree Test with One Input Stuck High

A similar effect occurs if two adjacent inputs are shorted

together. The example in Figure 61 assumes that the current

sink capability of the circuit driving the inputs is considerably

higher than the source capability, so the inputs are low if either

is low, but high only if both are high.

When GPIO12 goes high the output should go high. But

because GPIO12 and GPIO11 are shorted, they both go high

together, causing a missing pulse in the output pattern.

GPIO16

GPIO15

GPIO14

GPIO13

GPIO12

GPIO11

GPIO10

GPIO9

GPIO8

FAN0

FAN1

NTESTOUT

Figure 61. NAND Tree Test with Two Inputs Shorted

USING THE ADM1026

When power is first applied, the ADM1026 performs a power-

on reset on all its registers (not EEPROM), which sets them to

default conditions as shown in Table 12. In particular, note that

all GPIO pins are configured as inputs to avoid possible

conflicts with circuits trying to drive these pins.

The ADM1026 can also be initialized at any time by writing a

1 to Bit 7 of Configuration Register 1, which sets some registers

to their default power-on conditions. This bit should be cleared

by writing a 0 to it.

After power-on, the ADM1026 must be configured to the user’s

specific requirements. This consists of

•

Writing values to the limit registers.

•

Configuring Pins 3 to 6, and 9 to 12 as fan inputs or GPIO,

using Configuration Register 2 (Address 01h).

•

Setting the fan divisors using the fan divisor registers

(Addresses 02h and 03h).

•

Configuring the GPIO pins for input/output polarity, using

GPIO Configuration Registers 1 to 4 (Addresses 08h to

0Bh) and Bits 6 and 7 of Configuration

•

Setting mask bits in Mask Registers 1 to 6 (Addresses 18h

to 1Dh) for any inputs that are to be masked out.

•

Setting up Configuration Registers 1 and 3, as described in

Table 9 and Table 10.

Table 9. Configuration Register 1

Bit

Description

Controls the monitoring loop of the ADM1026.

Setting Bit 0 low stops the monitoring loop and puts

the ADM1026 into low power mode and reduces

power consumption. Serial bus communication is still

possible with any register in the ADM1026 while in

low power mode. Setting bit 0 high starts the

monitoring loop.

Enables or disables the INT interrupt output. Setting

Bit 1 high enables the INT output, setting Bit 1 low

disables the output.

Used to clear the INT interrupt output when set high.

GPIO pins and interrupt status register contents are

not affected.

Configures Pins 27 and 28 as the second external

temperature channel when 0, and as AIN8 and AIN9

when set to 1.

Enables the THERM output when set to 1.

Enables automatic fan speed control on the DAC

output when set to 1.

Enables automatic fan speed control on the PWM

output when set to 1.

Performs a soft reset when set to 1.

Table 10. Configuration Register 3

Bit

Description

Configures Pin 42 as GPIO when set to 1 or as THERM

when cleared to 0.

Clears the CI latch when set to 1. Thereafter, a 0 must

be written to allow subsequent CI detection.

Selects VREF as 2.5 V when set to 1 or as 1.82 V when

cleared to 0.

3–5

Unused.

6, 7

Set up GPIO16 for direction and polarity.

EVAL-ADM1026EB Datasheet(PDF) 33 Page - Analog Devices

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