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EVAL-ADM1026EB Datasheet(PDF) 45 Page - Analog Devices |
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EVAL-ADM1026EB Datasheet(HTML) 45 Page - Analog Devices |
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45 / 56 page  ADM1026 Rev. A | Page 45 of 56 Table 46. Register 21h, Status Register 2 (Power-On Default 00h) Bit Name R/W Description 0 AIN0 Status = 0 R 1, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous conversion cycle;0 otherwise. 1 AIN1 Status = 0 R 1, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous conversion cycle;0 otherwise. 2 AIN2 Status = 0 R 1, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous conversion cycle;0 otherwise. 3 AIN3 Status = 0 R 1, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous conversion cycle;0 otherwise. 4 AIN4 Status = 0 R 1, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous conversion cycle;0 otherwise. 5 AIN5 Status = 0 R 1, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous conversion cycle;0 otherwise. 6 AIN6 Status = 0 R 1, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous conversion cycle;0 otherwise. 7 AIN7 Status = 0 R 1, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous conversion cycle;0 otherwise. Table 47. Register 22h, Status Register 3 (Power-On Default 00h) Bit Name R/W Description 0 FAN0 Status 1 = 0 R 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise. 1 FAN1 Status 1 = 0 R 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise. 2 FAN2 Status 1 = 0 R 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise. 3 FAN3 Status 1 = 0 R 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise. 4 FAN4 Status 1 = 0 R 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise. 5 FAN5 Status 1 = 0 R 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise. 6 FAN6 Status 1 = 0 R 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise. 7 FAN7 Status 1 = 0 R 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise. Table 48. Register 23h, Status Register 4 (Power-On Default 00h) Bit Name R/W Description 0 Int Temp Status = 0 R 1, if Int value is above the high limit or below the low limit on the previous conversion cycle, 0 otherwise. This bit is set (once only) if a THERM mode is engaged as a result of int temperature readings exceeding the Int THERM limit. This bit is also set (once only) if THERM mode is disengaged as a result of internal temperature readings going 5°C below Int THERM limit. 1 VBAT Status = 0 R 1, if VBAT value is above the high limit or below the low limit on the previous conversion cycle, 0 otherwise. 2 AIN8 Status = 0 R 1, if AIN8 value is above the high limit or below the low limit on the previous conversion cycle, 0 otherwise. 3 THERM Status = 0 R This bit is set (once only) if a THERM mode is engaged as a result of temperature readings exceeding the THERM limits on any channel. This bit is also set (once only) if THERM mode is disengaged as a result of temperature readings going 5°C below THERM limits on any channel. 4 AFC Status = 0 R This bit is set (once only) if the fan turns on when in automatic fan speed control (AFC) mode as a result of a temperature reading exceeding TMIN on any channel. This bit is also set (once only) if the fan turns off when in automatic fan speed control mode. 5 Unused R Unused. Reads back 0. 6 CI Status = 0 R This bit latches a chassis intrusion event. 7 GPIO16 Status = 0 R When GPIO16 is configured as an input, this bit is set when GPIO16 is asserted. (Asserted may be active high or active low depending on the setting in GPIO configuration register.) R/W When GPIO16 is configured as an output, setting this bit asserts GPIO16. (Asserted may be active high or active low depending on setting in GPIO configuration register.) |
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